Electrical Characteristics of Metal - (La0.27Y0.73)2O3 - Silicon Capacitors

2003 ◽  
Vol 786 ◽  
Author(s):  
E. J. Preisler ◽  
N. A. Bojarczuk ◽  
S. Guha
Keyword(s):  
Silicon Oxide ◽  
Oxide Thickness ◽  
Electrical Characteristics ◽  
Metal Insulator ◽  
Silicon Oxide Layer ◽  
Flat Interface ◽  
Capacitance Voltage ◽  
Mis Capacitors ◽  
Atomically Flat ◽  
Density Of Interface States

ABSTRACTAn investigation of metal-insulator-silicon capacitors, utilizing single crystal (La0.27Y0.73)2O3 as the insulator is presented. Crystalline insulators are of interest because of the possibilities of obtaining an atomically flat interface and entirely eliminating the presence of dangling bonds at the interface.Capacitance – voltage measurements performed on MIS capacitors demonstrate a dielectric constant of 11.4 and suggest the absence of any interfacial silicon oxide layer. The equivalent oxide thickness of the sample with the thinnest dielectric layer is 15 Å. The density of interface states for the best samples is found to be in the mid 1012 cm−2eV−1 range and did not vary significantly after typical annealing treatments.

Dynamic growth mechanism and interface structure of crystalline zirconia on silicon

2002 ◽  
Vol 745 ◽  
Author(s):  
S J Wang ◽  
A C H Huan ◽  
C K Ong
Keyword(s):  
Photoelectron Spectroscopy ◽  
Silicon Oxide ◽  
Present Report ◽  
Amorphous Layer ◽  
Oxide Thickness ◽  
Interface State ◽  
Interface Structure ◽  
State Density ◽  
Silicon Oxide Layer ◽  
Crystalline Oxide

ABSTRACTIn present report, we have studied the initial stage of the growth of crystalline yttria-stabilized zirconia (YSZ) films on the natively oxidized Si (100) wafer by pulsed-laser deposition. X-ray photoelectron spectroscopy (XPS) and high-resoluti on transmission electron microscopy (HRTEM) show that, for the first few monolayers of crystalline YSZ deposited on Si (100), the dynamic processes appear to be the decomposition of SiO2 to SiO, the formation of ZrO2, and the desorption of SiO. The native amorphous silicon oxide layer is removed completely with the continued deposition of YSZ and the oxygen in this layer is used as oxygen source for forming stable crystalline oxide film. XPS depth profile and HRTEM investigation showed that the interface of crystalline YSZ film in contact with silicon was found to be atomically sharp and commensurately crystallized without an amorphous layer. The interface structure is suggested to have a sequence of-Si-O-Zr-O-. For the film with electrical equivalent oxide thickness 1.46 nm, the leakage current is about 1.1×10-3 A/cm2 at 1 V bias voltage. The hysteresis and interface state density in this film are measured to be less than 10 mV and 2.0×1011eV-1cm-2.

Effects of a Post-Oxidation Annealing in Nitrous Oxide on the Morphological and Electrical Properties of SiO2/4H-SiC Interfaces

2013 ◽  
Vol 740-742 ◽  
pp. 719-722 ◽  
Author(s):  
Lukas K. Swanson ◽  
Patrick Fiorenza ◽  
Filippo Giannazzo ◽  
Fabrizio Roccaforte
Keyword(s):  
Nitrous Oxide ◽  
Electrical Characterization ◽  
Mos Capacitors ◽  
Flat Interface ◽  
Transmission Electron ◽  
Nanoscale Characterization ◽  
Atomically Flat ◽  
Density Of Interface States ◽  
Insight Into

This work reports on the morphological, structural and electrical effects of a nitrous oxide (N2O) ambient post-oxidation annealing (POA) of the SiO2/4H-SiC interface. In particular, a conventional electrical characterization of MOS capacitors showed that nitrous oxide POA reduces the presence of both fixed oxide charge and the density of interface states. A local atomically flat interface was observed by transmission electron microscopy with only a moderate step bunching observed at a macroscopic scale. A novel nanoscale characterization approach via scanning spreading resistance microscopy resolved local electrical changes induced at the SiC surface exposed to N2O POA. This result subsequently revealed additional insight into the mechanism for the improved device performance subjected to N2O POA treatment.

Temperature Dependent C-V Characteristics of YBCO/YSZ/Si MIS Capacitors

1992 ◽  
Vol 275 ◽  
Author(s):  
Jianmin Qiao ◽  
Eric M. Ajimine ◽  
Paresh P. Patel ◽  
Marco A. Segovia ◽  
Cary Y. Yang ◽  
...  
Keyword(s):  
Temperature Cycling ◽  
Temperature Dependent ◽  
Metal Insulator ◽  
Thermally Activated ◽  
Threshold Voltages ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Mobile Ions ◽  
Mis Capacitors ◽  
Thermally Activated Process

ABSTRACTMetal-insulator-semiconductor capacitors are fabricated from a YBa2Cu3O7-δ (YBCOVYttria-Stabilized Zirconia(YSZ)/Si structure. Current-voltage(I-V) measurements reveal that thicker YBCO films(≤150Å) tend to result in more stable capacitors. Results of capacitance-voltage(C-V) measurements during bias-temperature cycling suggest the presence of a thermally activated process in the YSZ and/or YSZ/Si interface. This process is probably related to trapping/detrapping mechanisms in the SiOx, layer formed between YSZ and Si. It is shown that the distribution of mobile ions in YSZ can be “set” with biases at room temperature and then “frozen” by lowering the temperature, giving rise to adjustable threshold voltages at 80K.

Detecting Impurities in the Ultra Thin Silicon Oxide Layer By Hg-Schottky Capacitance–Voltage (CV) Method

2001 ◽  
Vol 670 ◽  
Author(s):  
D. Liu ◽  
Q. Wang ◽  
H. Paravi ◽  
V. Drobny ◽  
J. Moquin
Keyword(s):  
Oxide Layer ◽  
Silicon Oxide ◽  
Gate Oxide ◽  
New Method ◽  
Silicon Oxide Layer ◽  
Oxide Structure ◽  
Metal Impurities ◽  
Capacitance Voltage ◽  
Thin Silicon ◽  
Wafer Processing

ABSTRACTDetecting impurities or contaminations in the ultra thin silicon oxide layer is one of the most serious challenges in wafer processing as device is scaled down toward deep sub-micron. These impurities or contaminations will create charge traps in the oxide layer and degrade gate oxide integrity (GOI). The MOS Capacitance-Voltage method which has been used to study the electrical charges in relative thicker oxide layer (> 5 nm) cannot detect, however, these contaminations related charges in the ultra thin silicon oxide layer. In this article, a new method has been developed to determine the electrical charges associated with the contaminations in an ultra thin oxide layer using Hg-Schottky capacitance-voltage method. The oxide layers of 1.2 nm in thickness with and without Cu-contamination have been tested with this new method. The results show that the new method can be used to qualitatively identify the electrical charges trapped in the ultra thin silicon oxide layer and the trapping levels associated with the contamination. The interactions among sub-stochiometric oxide structure and electron traps introduced by the metal impurities have been discussed.

Selection, Growth, and Characterization of Gate Insulators on Mocvd Gallium Nitride for the Use in High Power Field Effect Devices

1997 ◽  
Vol 482 ◽  
Author(s):  
R. J. Therrien ◽  
O. H. Nam ◽  
M. D. Bremser ◽  
K. Lithicum ◽  
H. Nimii ◽  
...  
Keyword(s):  
Chemical Vapor ◽  
Gate Insulator ◽  
Electrical Characteristics ◽  
High Power Field ◽  
Metal Insulator ◽  
Chemical Vapor Deposited ◽  
Field Effect Devices ◽  
Mis Capacitors ◽  
Good Agreement

AbstractMetal-insulator-semiconductor (MIS) capacitors have been fabricated on n-type GaN (0001) films using thermally grown Ga2O3, remote plasma enhanced chemical vapor deposited (RPECVD) SiO2, and molecular beam epitaxy (MBE) AIN as the gate insulator and Al as the gate electrode. Each GaN epitaxial layer was grown by organometallic chemical vapor deposition (OMCVD) on a 6H-SiC(0001) substrate on which was previously deposited a 1000Å buffer layer of AIN. Nitrogen-free polycrystalline films of Ga2O3 were grown on the GaN. Capacitancevoltage measurements of capacitors fabricated from this oxide showed distinct depletion and accumulation regions with significant leakage. The AIN and SiO2 capacitors demonstrated better electrical characteristics than the Ga2O3 because of lower leakage. The RPECVD SiO2/GaN heterostructures, in particular, showed good agreement with the curves calculated for an ideal oxide and a small amount of hysteresis.

Analysis of failure of C-V characteristics of MIS structure with SiO2 passivation layer deposited on InSb substrate via Raman spectroscopy

2014 ◽  
Vol 1670 ◽  
Author(s):  
Chulkyun Seok ◽  
Sujin Kim ◽  
Jaeyel Lee ◽  
Sehun Park ◽  
Yongjo Park ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Electrical Properties ◽  
Deposition Temperature ◽  
Silicon Oxide ◽  
Oxide Semiconductor ◽  
Mis Structure ◽  
Metal Insulator ◽  
Capacitance Voltage ◽  
Resonant Raman ◽  
Mos Structures

ABSTRACTThe effect of interfacial phases on the electrical properties of Au/Ti/SiO2/InSb metal-insulator (oxide)-semiconductor (MIS or MOS) structures was investigated by capacitance-voltage (C-V) measurements. With increasing the deposition temperature of silicon oxide from 100 to 350°C using PECVD, the change in the interfacial phases between SiO2 and InSb were analyzed by resonant Raman spectroscopy to verify the relation between the breakdown of C-V characteristics and the change of interfacial phases. The shape of C-V characteristics was dramatically changed when the deposition temperature was above 300°C. The C-V measurements and Raman spectra represented that elemental Sb accumulation resulted from the chemical reaction of Sb oxide with InSb substrate was responsible for the failure in the C-V characteristics of MIS structure.

Effects of a Post-Oxidation Annealing in Nitrous Oxide on the Morphological and Electrical Properties of SiO2/4H-SiC Interfaces

2013 ◽  
Vol 740-742 ◽  
pp. 715-718 ◽  
Author(s):  
Lukas K. Swanson ◽  
Patrick Fiorenza ◽  
Filippo Giannazzo ◽  
S. Alessandrino ◽  
S. Lorenti ◽  
...  
Keyword(s):  
Nitrous Oxide ◽  
Electrical Characterization ◽  
Mos Capacitors ◽  
Flat Interface ◽  
Transmission Electron ◽  
Nanoscale Characterization ◽  
Atomically Flat ◽  
Density Of Interface States ◽  
Insight Into

This work reports on the morphological, structural and electrical effects of a nitrous oxide (N2O) ambient post-oxidation annealing (POA) of the SiO2/4H-SiC interface. In particular, a conventional electrical characterization of MOS capacitors showed that nitrous oxide POA reduces the presence of both fixed oxide charge and the density of interface states. A local atomically flat interface was observed by transmission electron microscopy with only a moderate step bunching observed at a macroscopic scale. A novel nanoscale characterization approach via scanning spreading resistance microscopy resolved local electrical changes induced at the SiC surface exposed to N2O POA. This result subsequently revealed additional insight into the mechanism for the improved device performance subjected to N2O POA treatment.

Oxidation of Silicon and Nitridaticn of SiO2 by Rapid Thermal Processes

1987 ◽  
Vol 92 ◽  
Author(s):  
N. Chan Tung ◽  
Y. Caratini ◽  
J.L. Buevoz
Keyword(s):  
Oxide Thickness ◽  
Breakdown Field ◽  
Thermal Processes ◽  
Electrical Characteristics ◽  
Gate Oxides ◽  
A Value ◽  
High Resolution Tem ◽  
S Period ◽  
Thermal Nitridation ◽  
Mis Capacitors

ABSTRACTThin gate oxides of 30 to 150 Å have been grown in a rapid thermal annealing machine. Experiments were performed in the temperature range of 1000 to 1250°C for an oxidation time of 5 to 60 s. The fairly extensive kinetics data show that linear growth occurs with an activation energy Ea of 1.4 eV for the 5-60 s period. The oxide homogeneity was evaluated and gave a value of 1.9 A for a mean oxide thickness of 102 A. The electrical characteristics of Al-gate capacitors were assessed by C-V and I-V measurements. Rapid thermal nitridation of a 96 A SiO2 has been performed at a temperature of 1150°C for a nitridaticn time up to 150 s. An average breakdown field of 14.6 MV/cm has been obtained for MIS capacitors. High resolution TEM show a good interface SioXNY-Si.

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