Numerical Simulation and Experiment of a High-Efficiency Tunnel Oxide Passivated Contact (TOPCon) Solar Cell Using a Crystalline Nanostructured Silicon-Based Layer

We report on the tunnel oxide passivated contact (TOPCon) using a crystalline nanostructured silicon-based layer via an experimental and numerical simulation study. The minority carrier lifetime and implied open-circuit voltage reveals an ameliorated passivation property, which gives the motivation to run a simulation. The passivating contact of an ultra-thin silicon oxide (1.2 nm) capped with a plasma enhanced chemical vapor deposition (PECVD) grown 30 nm thick nanocrystalline silicon oxide (nc-SiOx), provides outstanding passivation properties with low recombination current density (Jo) (~1.1 fA/cm2) at a 950 °C annealing temperature. The existence of a thin silicon oxide layer (SiO2) at the rear surface with superior quality (low pinhole density, Dph < 1 × 10−8 and low interface trap density, Dit ≈ 1 × 108 cm−2 eV−1), reduces the recombination of the carriers. The start of a small number of transports by pinholes improves the fill factor (FF) up to 83%, reduces the series resistance (Rs) up to 0.5 Ω cm2, and also improves the power conversion efficiency (PEC) by up to 27.4%. The TOPCon with a modified nc-SiOx exhibits a dominant open circuit voltage (Voc) of 761 mV with a supreme FF of 83%. Our simulation provides an excellent match with the experimental results and supports excellent passivation properties. Overall, our study proposed an ameliorated knowledge about tunnel oxide, doping in the nc-SiOx layer, and additionally about the surface recombination velocity (SRV) impact on TOPCon solar cells.

Transformation of CaSi overgrowth domains to the CaSi2 crystal phase via vacuum annealing

The phase transformation of overgrown CaSi crystal on an (00l)-oriented epitaxial CaSi2 film was studied using high-angle annular dark-field scanning transmission electron microscopy. After annealing at 450°C under vacuum conditions, the CaSi domain transformed to the CaSi2 phase with thin Si layers. The transformed CaSi2 crystal formed epitaxially along the under-layer epitaxial CaSi2 film. The results suggest that Ca atoms in the overgrown CaSi domain diffused to the outermost passivated silicon oxide layer during the low-temperature vacuum anneal.

On the Utility of Coated POSS-Polyimides for Vehicles in Very Low Earth Orbit (VLEO)

The environment encountered by space vehicles in very low Earth orbit (VLEO, 180 – 350 km altitude) contains predominantly atomic oxygen (AO) and molecular nitrogen (N2), which collide with ram surfaces at relative velocities of ~7.5 km s-1. Structural, thermal-control, and coating materials containing organic polymers are particularly susceptible to AO attack at these high velocities, resulting in erosion, roughening, and degradation of function. Copolymerization or blending of a polymer with polyhedral oligomeric silsesquioxane (POSS) yields a material that can resist AO attack through the formation of a passivating silicon-oxide layer. Still, these hybrid organic/inorganic polymers become rough through AO reactions as the passivating layer is forming. Surface roughness may enhance satellite drag because it promotes energy transfer and scattering angle randomization during gas-surface collisions. As potential low-drag and AO-resistant materials, we have investigated POSS-containing films of clear and Kapton-like polyimides that have an atomically smooth AO-resistant coating of Al2O3 that is grown by atomic layer deposition (ALD). Coated and uncoated films were exposed to hyperthermal molecular beams containing atomic and molecular oxygen to investigate their AO resistance, and molecular beam-surface scattering studies were conducted to characterize the gas-surface scattering dynamics on pristine and AO-exposed surfaces to inform drag predictions. The AO erosion yield of Al2O3 ALD-coated films is essentially zero. Simulations of drag on a representative satellite structure that are based on the observed scattering dynamics suggest that the use of the Al2O3 ALD-coated POSS-polyimides on external satellite surfaces have the potential to reduce drag to less than half that predicted for diffuse scattering surfaces. These smooth and AO-resistant polymer films thus show promise for use in the extreme oxidizing and high-drag environment in VLEO.

Tailoring Morphology and Vertical Yield of Self-Catalyzed GaP Nanowires on Template-Free Si Substrates

Tailorable synthesis of III-V semiconductor heterostructures in nanowires (NWs) enables new approaches with respect to designing photonic and electronic devices at the nanoscale. We present a comprehensive study of highly controllable self-catalyzed growth of gallium phosphide (GaP) NWs on template-free silicon (111) substrates by molecular beam epitaxy. We report the approach to form the silicon oxide layer, which reproducibly provides a high yield of vertical GaP NWs and control over the NW surface density without a pre-patterned growth mask. Above that, we present the strategy for controlling both GaP NW length and diameter independently in single- or two-staged self-catalyzed growth. The proposed approach can be extended to other III-V NWs.

Maskless Lithography Using Silicon Oxide Etch-Stop Layer Induced by Megahertz Repetition Femtosecond Laser Pulses

In this study we report a new method for maskless lithography fabrication process by a combination of direct silicon oxide etch-stop layer patterning and wet alkaline etching. A thin layer of etch-stop silicon oxide of predetermined pattern was first generated by irradiation with high repetition (MHz) ultrafast (femtosecond) laser pulses in air and at atmospheric pressure. The induced thin layer of silicon oxide is used as an etch stop during etching process in alkaline etchants such as KOH. Our proposed method has the potential to enable low-cost, flexible, high quality patterning for a wide variety of application in the field of micro- and nanotechnology, this technique can be leading to a promising solution for maskless lithography technique. A Scanning Electron Microscope (SEM), optical microscopy, Micro-Raman, Energy Dispersive X-ray (EDX) and X-ray diffraction spectroscopy were used to analyze the silicon oxide layer induced by laser pulses.

Deformation Behavior of Various Interconnection Structures Using Fine Pitch Microelectromechanical Systems (MEMS) Vertical Probe

Recently, fine pitch wafer level packaging (WLP) technologies have drawn a great attention in the semiconductor industries. WLP technology uses various interconnection structures including microbumps and through-silicon-vias (TSVs). To increase yield and reduce cost, there is an increasing demand for wafer level testing. Contact behavior between probe and interconnection structure is a very important factor affecting the reliability and performance of wafer testing. In this study, with a MEMS vertical probe, we performed systematic numerical analysis of the deformation behavior of various interconnection structures, including solder bump, copper (Cu) pillar bump, solder capper Cu bump, and TSV. During probing, the solder ball showed the largest deformation. The Cu pillar bump also exhibited relatively large deformation. The Cu bump began to deform at OD of 10 μm. At OD of 20 μm, bump pillar was compressed, and the height of the bump decreased by 8.3%. The deformation behavior of the solder capped Cu bump was similar to that of the solder ball. At OD of 20 μm, the solder and Cu bumps were largely deformed, and the total height was reduced by 11%. The TSV structure showed the lowest deformation, but exerted the largest stress on the probe. In particular, copper protrusion at the outer edge of the via was observed, and very large shear stress was generated between the via and the silicon oxide layer. In summary, when probing various interconnection structures, the probe stress is less than that when using an aluminum pad. On the other hand, deformation of the structure is a critical issue. In order to minimize damage to the interconnection structure, smaller size probes or less overdrive should be used. This study will provide important guidelines for performing wafer-level testing and minimizing damage of probes and interconnection structures.