Simulation and Comparison of Current Voltage Characteristics of Si and Ge based Bio Field Effect Transistor by Varying Oxide Thickness to Get Better Sensitivity

Aim: The current voltage characteristics of Silicon based BIOFET and Germanium based BIOFET are simulated by varying their oxide thickness ranging from 1nm to 100nm. Materials and Methods: The electrical conductance of Silicon based BIOFET (n=320) was compared with Germanium based BIOFET (n=320) by varying oxide thickness ranging from 1nm to 100nm in the NanoHub© tool simulation environment. Results: Germanium based BIOFET has significantly higher conductance than Silicon based BIOFET. The optimal gate oxide thickness for maximum conductivity was 1nm for Silicon based BIOFET and 35nm for Germanium based BIOFET. Conclusion: Within the limits of the study, Germanium based BIOFET with oxide thickness of 35nm offers the best conductivity.

Simulation of Carbon Nanotube based Field Effect Transistor by Varying Gate Oxide Thickness to Explore its Electrical Property and Compare it with Standard Mosfet

Aim: The current and voltage characteristics of CNTFET and MOSFET are simulated by varying their gate oxide thickness ranging from 3.5nm to 11.5nm. Materials and Methods: The electrical conductance of CNTFET (n = 320) was compared with MOSFET (n = 320) by varying gate oxide thickness ranging from 3.5nm to 11.5nm in the NanoHUB© tool simulation environment. Results: CNTFET has significantly higher conductance (12.52 mho) than MOSFET (12.07 mho). The optimal thickness for maximum conductivity was 4nm for CNTFET and 3.5 nm for MOSFET. Conclusion: Within the limits of this study, CNTFET with the gate oxide thickness of 4 nm offers the best conductivity.

Atomic-scale ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to the adoption of high-κ dielectric HfO2 in the gate stack in 2008, which remains as the material of choice to date. Here, we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors and scaled down to ~ 20 Å, the same gate oxide thickness required for high performance transistors. The overall EOT (equivalent oxide thickness) in metal-oxide-semiconductor capacitors is equivalent to ~ 6.5 Å effective SiO2 thickness, which is, counterintuitively, even smaller than the interfacial SiO2 thickness (8.0-8.5 Å) itself. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-κ dielectric gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. Therefore, our work demonstrates that HfO2-ZrO2 multilayers with competing ferroelectric-antiferroelectric order, stabilized in the 2 nm thickness regime, provides a new path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO2-based high-κ dielectrics.

Charge Based Current–Voltage Model for the Silicon on Insulator Junctionless Field-Effect Transistor

In this study, we propose an accurate and simple current–voltage model for an SOI-JLFET based on a solution of the Poisson equation. The model is divided into three regions: accumulation, accumulation–depletion, and depletion. The charge density in each region is calculated with the Poisson equation and region-specific boundary conditions, and then the current is obtained by integrating the charge density with consideration of the Vds effect. The proposed model, which was implemented in HSPICE using Verilog-A, was validated using TCAD simulation for various physical conditions such as SOI channel thickness, gate oxide thickness, and channel doping concentration type. According to simulation results by the error rate calculation, our model shows more than 90% accuracy.

Experimental Study of Switching and Short-Circuit Performance of 1.2 kV 4H-SiC Accumulation and Inversion Channel Power MOSFETs

This paper compares the static and dynamic performance of 1.2 kV 4H-SiC ACCUFETs and INVFETs with identical channel length (0.5 μm) and gate oxide thickness (55 nm). It is demonstrated for the first time that ACCUFETs have lower total switching losses in comparison to the INVFETs. ACCUFETs are therefore superior devices for applications due to their lower specific on-resistance and overall switching losses. However, short circuit tests conducted on the devices show that ACCUFETs have a smaller short-circuit time (tSC) in comparison the INVFETs due to their higher short-circuit current.