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Wafer Edge Process Integration and Defect Inspection with the Immersion Lithography Process
ECS Transactions
◽
10.1149/06001.0847ecst
◽
2014
◽
Vol 60
(1)
◽
pp. 847-853
◽
Cited By ~ 1
Author(s):
Q. Ni
◽
H. Chen
◽
K. Wang
◽
Y. Long
◽
R. Fang
Keyword(s):
Process Integration
◽
Defect Inspection
◽
Immersion Lithography
◽
Lithography Process
◽
Edge Process
◽
Wafer Edge
Download Full-text
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Characterization of film cut position at wafer bevel for effective immersion lithography process
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◽
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Defectivity improvement by modified wafer edge treatment in immersion lithography
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◽
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◽
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a novel positive tone development method for defect reduction in the semiconductor 193 nm immersion lithography process
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◽
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◽
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◽
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◽
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◽
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◽
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◽
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◽
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◽
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Multilayer BARCs for hyper-NA immersion lithography process
10.1117/12.711382
◽
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◽
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◽
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◽
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◽
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◽
...
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◽
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Transfer mechanism of defects on topcoat to resist pattern in immersion lithography process and effects on etching process
10.1117/12.711281
◽
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◽
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◽
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◽
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Keyword(s):
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◽
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◽
Immersion Lithography
◽
Lithography Process
Download Full-text
Focus, dynamics, and defectivity performance at wafer edge in immersion lithography
10.1117/12.771598
◽
2008
◽
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◽
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◽
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◽
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Immersion Lithography
◽
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Influence of Immersion Lithography on Wafer Edge Defectivity
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◽
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◽
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◽
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◽
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◽
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◽
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Film stacking architecture for immersion lithography process
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◽
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◽
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◽
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◽
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◽
Kazuhito Shigemori
◽
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◽
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Immersion Lithography
◽
Lithography Process
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Innovative metrology for wafer edge defectivity in immersion lithography
10.1117/12.713347
◽
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◽
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◽
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◽
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◽
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◽
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◽
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◽
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Low-loss, flat-topped and spectrally uniform silicon-nanowire-based 5th-order CROW fabricated by ArF-immersion lithography process on a 300-mm SOI wafer
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◽
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◽
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◽
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◽
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◽
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◽
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◽
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◽
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◽
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◽
...
Keyword(s):
Silicon Nanowire
◽
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◽
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◽
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Download Full-text
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