The Effect of Wafer Edge Cu Contamination on FinFET Devices

The effect of copper (Cu) contamination inside the Si substrate from the wafer edge to the nearby devices has been investigated. After the Cu seed layer deposition, Cu contacted directly with Si at wafer edge where dielectric isolation layer was removed. Under the routine BEOL metallization and after the capping SiON/Si2O layers, SEM and AES analysis located a strip of islets of Cu contaminants. TEM analysis revealed that the seed Cu had interacted with Si substrate to form a stable ?-Cu3Si intermetallic compound that appeared to be planted into the Si substrate at the surface. SIMS analysis from the wafer backside, opposite to this strip of ?-Cu3Si islets at front, showed no Cu detection even after the majority of the backside Si was removed by grinding. Electrical nano-probing did not discern any parametric drift for the nanometer FinFET devices on chips near the edge surface of massive ?-Cu3Si islets in comparison with a reference chip from an uncontaminated wafer center. These results indicate that the formation of ?-Cu3Si, with a well-defined crystalline structure and a relatively stable stoichiometry, immobilizes Cu diffusion inside the Si substrate. In other word, the impact of Cu diffusion in Si has no effect on device performances as long as ?-Cu3Si is not directly formed in the FinFET channel or presents to short any structures within the chip.

Efficient Identification of Wafer Edge’s Defect with Volume Diagnosis Analysis and Plasma-FIB Planar Deprocessing

In the failure analysis (FA) of modern semiconductor logic device manufactured in foundry fab, efficient identification of wafer edge’s defect was studied by using volume diagnosis analysis and plasma-focused ion beam (FIB) planar deprocessing. As the chip from wafer edge has multiple defective locations, there is the limitation of the conventional FA work to identify them. Here, we used volume diagnosis analysis to identify the multiple defective locations within chip and plasma-FIB planar deprocessing to delayer those locations and find out defects. The actual FA work verified that new workflow successfully identified the different defects from different layers from the chip of wafer edge and efficiently accelerated the quantity of FA results, importantly leading to more representative status of inline defect.