Metamaterial-Engineered Silicon Beam Splitter Fabricated with Deep UV Immersion Lithography

Subwavelength grating (SWG) metamaterials have garnered a great interest for their singular capability to shape the material properties and the propagation of light, allowing the realization of devices with unprecedented performance. However, practical SWG implementations are limited by fabrication constraints, such as minimum feature size, that restrict the available design space or compromise compatibility with high-volume fabrication technologies. Indeed, most successful SWG realizations so far relied on electron-beam lithographic techniques, compromising the scalability of the approach. Here, we report the experimental demonstration of an SWG metamaterial engineered beam splitter fabricated with deep-ultraviolet immersion lithography in a 300-mm silicon-on-insulator technology. The metamaterial beam splitter exhibits high performance over a measured bandwidth exceeding 186 nm centered at 1550 nm. These results open a new route for the development of scalable silicon photonic circuits exploiting flexible metamaterial engineering.

Large-area metasurface on CMOS-compatible fabrication platform: driving flat optics from lab to fab

A metasurface is a layer of subwavelength-scale nanostructures that can be used to design functional devices in ultrathin form. Various metasurface-based optical devices – coined as flat optics devices – have been realized with distinction performances in research laboratories using electron beam lithography. To make such devices mass producible at low cost, metasurfaces over a large area have also been defined with lithography steppers and scanners, which are commonly used in semiconductor foundries. This work reviews the metasurface process platforms and functional devices fabricated using complementary metal-oxide-semiconductor-compatible mass manufacturing technologies. Taking both fine critical dimension and mass production into account, the platforms developed at the Institute of Microelectronics (IME), A*STAR using advanced 12-inch immersion lithography have been presented with details, including process flow and demonstrated optical functionalities. These developed platforms aim to drive the flat optics from lab to fab.

Basic approaches to simulation of resist mask formation in computational lithography

Main currently used resist mask formation models and problems solved have been overviewed. Stages of "full physical simulation" have been briefly analyzed based on physicochemical principles for conventional diazonapthoquinone (DNQ) photoresists and chemically enhanced ones. We have considered the concepts of the main currently used compact models predicting resist mask contours for full-scale product topologies, i.e., VT5 (Variable Threshold 5) and CM1 (Compact Model 1). Computation examples have been provided for full and compact resist mask formation models. Full resist mask formation simulation has allowed us to optimize the lithographic stack for a new process. Optimal thickness ratios have been found for the binary anti-reflecting layers used in water immersion lithography. VT5 compact model calibration has allowed us to solve the problem of optimal calibration structure sampling for maximal coverage of optical image parameters space while employing the minimal number of structures. This problem has been solved using cluster analysis. Clustering has been implemented using the k-means method. The optimum sampling is 300 to 350 structures, the rms error being 1.4 nm which is slightly greater than the process noise for 100 nm structures. The use of SEM contours for VT5 model calibration allows us to reduce the rms error to 1.18 nm for 40 structures.