Innovative metrology for wafer edge defectivity in immersion lithography

2007 ◽  
Author(s):  
I. Pollentier ◽  
F. Iwamoto ◽  
M. Kocsis ◽  
A. Somanchi ◽  
F. Burkeen ◽  
...  
Keyword(s):  
Immersion Lithography ◽  
Wafer Edge

Defectivity improvement by modified wafer edge treatment in immersion lithography

2009 ◽  
Author(s):  
Masafumi Fujita ◽  
Takao Tamura ◽  
Naka Onoda ◽  
Takayuki Uchiyama
Keyword(s):  
Immersion Lithography ◽  
Edge Treatment ◽  
Wafer Edge

Wafer Edge Process Integration and Defect Inspection with the Immersion Lithography Process

2014 ◽  
Vol 60 (1) ◽  
pp. 847-853 ◽  
Author(s):  
Q. Ni ◽  
H. Chen ◽  
K. Wang ◽  
Y. Long ◽  
R. Fang
Keyword(s):  
Process Integration ◽  
Defect Inspection ◽  
Immersion Lithography ◽  
Lithography Process ◽  
Edge Process ◽  
Wafer Edge

Focus, dynamics, and defectivity performance at wafer edge in immersion lithography

2008 ◽  
Author(s):  
Takao Tamura ◽  
Naka Onoda ◽  
Masafumi Fujita ◽  
Takayuki Uchiyama
Keyword(s):  
Immersion Lithography ◽  
Wafer Edge

scholarly journals Influence of Immersion Lithography on Wafer Edge Defectivity

Lithography ◽  
10.5772/8169 ◽  
2010 ◽  
Author(s):  
K. Jami ◽  
I. Pollentier ◽  
S. Vedula ◽  
G. Blumenstock
Keyword(s):  
Immersion Lithography ◽  
Wafer Edge

Trace Metallic Contamination Analysis on Wafer Edge and Bevel by TXRF and VPD-TXRF

2009 ◽  
Vol 145-146 ◽  
pp. 105-108 ◽  
Author(s):  
Hikari Takahara ◽  
Ken Tsugane
Keyword(s):  
Integrated Circuits ◽  
Water Drop ◽  
Semiconductor Industry ◽  
Wafer Surface ◽  
Reaction Products ◽  
Immersion Lithography ◽  
High K ◽  
Edge Exclusion ◽  
Wafer Edge ◽  
Metallic Contamination

In the semiconductor industry, the edge exclusion of processed wafers is decreasing to accommodate more integrated circuits. With this trend, there is a higher risk of detrimental contamination at the wafer edge and bevel making the monitoring for metallic contamination in these areas critical. Cross contamination from the edge and bevel can occur at many processing steps. For example, metals can spread from the wafer edge, bevel and backside to the wafer’s surface in a wet cleans process. In immersion lithography, the water drop that is scanned across the wafer could transport contamination from the edge and deposit it across the wafer surface. Contamination on wafer edge and bevel can have many origins; handling systems in every process tool, reaction products in etching, and residuals of new materials in high-k for CVD and PVD, for example. To know what metallic contamination is present, and to investigate the causes are essential for wafer edge control.

Wafer edge polishing process for defect reduction during immersion lithography

2008 ◽  
Author(s):  
Motoya Okazaki ◽  
Raymond Maas ◽  
Sen-Hou Ko ◽  
Yufei Chen ◽  
Paul Miller ◽  
...  
Keyword(s):  
Polishing Process ◽  
Defect Reduction ◽  
Immersion Lithography ◽  
Wafer Edge

Feasibility of 37-nm half-pitch with ArF high-index immersion lithography

2007 ◽  
Author(s):  
Yoshiyuki Sekine ◽  
Miyoko Kawashima ◽  
Eiji Sakamoto ◽  
Keita Sakai ◽  
Akihiro Yamada ◽  
...  
Keyword(s):  
High Index ◽  
Immersion Lithography

scholarly journals Novel high-index resists for 193-nm immersion lithography and beyond

2007 ◽  
Author(s):  
Idriss Blakey ◽  
Lan Chen ◽  
Bronwin Dargaville ◽  
Heping Liu ◽  
Andrew Whittaker ◽  
...  
Keyword(s):  
High Index ◽  
Immersion Lithography ◽  
193 Nm
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