Wafer level 3D system integration based on silicon interposers with through silicon vias

2012 ◽  
Author(s):  
K. Zoschke ◽  
H. Oppermann ◽  
C.-A Manier ◽  
I. Ndip ◽  
R. Puschmann ◽  
...  
Keyword(s):  
System Integration ◽  
Wafer Level ◽  
Through Silicon Vias ◽  
Silicon Vias

Reliable Design of Electroplated Copper Through Silicon Vias

2010 ◽  
Author(s):  
Xi Liu ◽  
Qiao Chen ◽  
Venkatesh Sundaram ◽  
Sriram Muthukumar ◽  
Rao R. Tummala ◽  
...  
Keyword(s):  
System Integration ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Interfacial Stress ◽  
Through Silicon Vias ◽  
Fabrication Defects ◽  
Reliable Design ◽  
Electroplated Copper ◽  
Key Enabling Technologies ◽  
Silicon Vias

Through-silicon vias (TSVs), being one of the key enabling technologies for 3D system integration, are being used in various 3D vertically stacked devices. As TSVs are relatively new, there is not enough information in available literature on the thermo-mechanical reliability of TSVs. Due to the high coefficient of thermal expansion (CTE) mismatch between Si and the Cu vias, “Cu pumping” will occur at high temperature and “Cu sinking” will occur at low temperature, which may induce large stress in SiO2, interfacial stress at Cu/SiO2 interface and plastic deformation in Cu core. The thermal-mechanical stress can potentially cause interfacial debonding, cohesive cracking in dielectric layers or Cu core, causing some reliability issues. Thus, in this paper, three-dimensional thermo-mechanical finite-element models have been built to analyze the stress/strain distribution in the TSV structures. A comparative analysis of different via designs, such as circular, square, and annular vias has been performed. In addition, defects due to fabrication such as voids in the Cu core during electroplating and Cu pad undercutting due to over-etching are considered in the models, and it is seen that these fabrication defects are detrimental to TSV reliability.

scholarly journals Over Molding Process Development for a Stacked Wafer-level Chip Scale Package with Through Silicon Vias (TSVs)

2012 ◽  
Vol 5 (1) ◽  
pp. 122-131 ◽  
Author(s):  
Yoshimi Takahashi ◽  
Rajiv Dunne ◽  
Masazumi Amagai ◽  
Yohei Koto ◽  
Shoichi Iriguchi ◽  
...  
Keyword(s):  
Process Development ◽  
Wafer Level ◽  
Molding Process ◽  
Through Silicon Vias ◽  
Chip Scale Package ◽  
Silicon Vias

scholarly journals Copper Electrodeposition in High Aspect Ratio Mesoscale Through-Silicon Vias: Scaling from Die Level to Wafer Level Plating

2020 ◽  
Vol MA2020-02 (25) ◽  
pp. 1787-1787
Author(s):  
Rebecca Pauline Schmitt ◽  
Lyle Alexander Menk ◽  
Matthew Jordan ◽  
Jason Christopher ◽  
Ehren Donel Baca ◽  
...  
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
Copper Electrodeposition ◽  
Wafer Level ◽  
Through Silicon Vias ◽  
Silicon Vias

Advanced Silicon Interposer for High density and High Integration Electronic Packages

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000865-000905
Author(s):  
SATORU KUMOCHI ◽  
Sumio Koiwa ◽  
Kosuke Suzuki ◽  
Yoshitaka Fukuoka
Keyword(s):  
System Integration ◽  
High Density ◽  
High Resistivity ◽  
Through Silicon Vias ◽  
Passive Device ◽  
Fine Pitch ◽  
Mems Technology ◽  
Cte Mismatch ◽  
Silicon Vias ◽  
Electrical Loss

As electronic product becomes smaller and lighter with an increasing number of function← the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Interposers will be needed more complicated structure for 2.5D , 3D package and MEMS, OEMEMS new heterogeneous package structure Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. [1] This paper presents the demonstration of Silicon Interposers with fine pitch through Silicon vias(TSV),with embedded passive device. We have developed the TSV interposer with redistribution layers on both sides using MEMS technology, high aspect ratio deep etching technology and filled Cu plating with deep through holes for cost reduction and low electrical loss. The TSV interposer with 400μm thick high resistivity Si, obtained without backside processing use of carriers. Excellent through via reliability was demonstrated, due to double side thick polymer insulator that buffers the stress created by CTE mismatch between glass, copper vias and copper traces, and TSV at 200μm pitch passed 1000 thermal cycles from −55°C to 125°C. We have evaluated high frequency transmission characteristic of Si through hole by the measurement S21 parameter. Highly insulating TSV resulted in insertion loss of less than 1dB at 20GHz. Thin film SiN capacitor as embedded passive device was built in surface of TSV interposer by via first and via last method. The capacitance and leakage current of capacitor was measured and compared with two types of fabrication method.

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