Successful void free gap fill of 3µm, high AR via middle, Through Silicon Vias at wafer level

2014 ◽  
Author(s):  
S. Thangaraju ◽  
L. England ◽  
M. Rabie ◽  
D. Zhang ◽  
G. Kumarapuram ◽  
...  
Keyword(s):  
Wafer Level ◽  
Through Silicon Vias ◽  
Silicon Vias

scholarly journals Over Molding Process Development for a Stacked Wafer-level Chip Scale Package with Through Silicon Vias (TSVs)

2012 ◽  
Vol 5 (1) ◽  
pp. 122-131 ◽  
Author(s):  
Yoshimi Takahashi ◽  
Rajiv Dunne ◽  
Masazumi Amagai ◽  
Yohei Koto ◽  
Shoichi Iriguchi ◽  
...  
Keyword(s):  
Process Development ◽  
Wafer Level ◽  
Molding Process ◽  
Through Silicon Vias ◽  
Chip Scale Package ◽  
Silicon Vias

scholarly journals Copper Electrodeposition in High Aspect Ratio Mesoscale Through-Silicon Vias: Scaling from Die Level to Wafer Level Plating

2020 ◽  
Vol MA2020-02 (25) ◽  
pp. 1787-1787
Author(s):  
Rebecca Pauline Schmitt ◽  
Lyle Alexander Menk ◽  
Matthew Jordan ◽  
Jason Christopher ◽  
Ehren Donel Baca ◽  
...  
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
Copper Electrodeposition ◽  
Wafer Level ◽  
Through Silicon Vias ◽  
Silicon Vias

Through Silicon Vias (TSVs) Technology for MEMS Packaging

2010 ◽  
Vol 154-155 ◽  
pp. 1695-1698 ◽  
Author(s):  
Kai Lin Pan ◽  
Jing Liu ◽  
Jiao Pin Wang ◽  
Jing Huang
Keyword(s):  
High Performance ◽  
Three Dimensional ◽  
Test Method ◽  
Wafer Level ◽  
Through Silicon Vias ◽  
Mems Packaging ◽  
Wafer Level Packaging ◽  
Critical Issues ◽  
Silicon Vias ◽  
Two Sides

Through silicon vias (TSVs) provide advanced vertical interconnections solutions for system-in-package (SiP) (such as chip to chip, chip to wafer, and wafer to wafer stacking), wafer-level packaging, interposer packaging. At present the shortest electrical path (vertical electrical feed through) between two sides of a silicon chip is one of the important applications. In order to achieve high density and high performance package, TSVs technology has been developed. And for three-dimensional (3D) MEMS (Microelectromechanical System) packaging, TSVs are the most important enabling technology. In this paper, some advantages of TSVs technology are described, and process flow of TSVs module is introduced firstly. Subsequently, a novel electricity test method of Non-Ideal Planes for TSVs is introduced. Finally, many critical issues and challenges of TSVs are reviewed.

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