Integration of two different gate oxide thicknesses in a 0.6-μm dual voltage mixed signal CMOS process

1995 ◽  
Vol 42 (1) ◽  
pp. 190-192 ◽  
Author(s):  
K.K. O ◽  
J. Yasaitis
Keyword(s):  
Gate Oxide ◽  
Cmos Process ◽  
Mixed Signal

Commercially developed mixed-signal CMOS process features for application in advanced ROICs in 0.18μm technology node

2012 ◽  
Author(s):  
Arjun Kar-Roy ◽  
Paul Hurwitz ◽  
Richard Mann ◽  
Yasir Qamar ◽  
Samir Chaudhry ◽  
...  
Keyword(s):  
Cmos Process ◽  
Mixed Signal ◽  
Technology Node

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration

2010 ◽  
Vol 39 ◽  
pp. 73-78 ◽  
Author(s):  
Jin Tao Jiang ◽  
Li Fang Ye ◽  
Jian Ping Hu
Keyword(s):  
Gate Oxide ◽  
Cmos Process ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Leakage Reduction ◽  
Nanometer Cmos ◽  
Benchmark Circuit ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Processes

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

A 3.2 mW Mixed-Signal Readout Circuit for an Organic Vertical Nano-Junctions Sensor

2016 ◽  
Author(s):  
Paul C.-P. Chao ◽  
Chin-I Su ◽  
Trong-Hieu Tran ◽  
Hsiao-Wen Zan
Keyword(s):  
Simple Structure ◽  
Low Cost ◽  
Time Response ◽  
Cmos Process ◽  
Readout Circuit ◽  
Readout System ◽  
Transient Time ◽  
Mixed Signal ◽  
Ammonia Detection ◽  
Signal Readout

A new sensitivity organic vertical nano-junctions (VNJ) sensor for ammonia detection and its readout system are presented in this study. The designed ammonia sensor, VNJP3HT diode, is a simple structure with real-time response, high reproducibility and low-cost sensor. Along with the designed sensor, a precision and robust readout circuit is designed and successfully implemented as the proposed chip in this study. To utilize for a novel organic bio-chip, a particular readout system is presented that can acquire signal, compute and display concentration values of ammonia without using microcontroller. The chip is fabricated by the TSMC 0.18-μm 1P6M 3.3V mixed-signal CMOS process technique for verification. Experiment results show that the average resolution is 70.48mV/log (ppm) in a short transient time response, 50 seconds, as compared to prior study, 200 seconds. Error rate, average noise and detection rate reliability are 2.86%, 123 μVrms, and 99.6%, respectively. This chip could be suitable for application in cars, cell phones, watches, etc.

Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology

2013 ◽  
Vol 10 (4) ◽  
pp. 150-154 ◽  
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Leakage Currents ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Operation Temperature

It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

Reliability Issues with Mixed-Signal CMOS Technology

1995 ◽  
Vol 391 ◽  
Author(s):  
Rajeeva Lahri ◽  
Hung-Sheng Chen ◽  
Ji Zhao ◽  
Kamesh Gadepally ◽  
C.S. Teng
Keyword(s):  
Analog Circuits ◽  
Analog Circuit ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Low Noise ◽  
Resistance Change ◽  
Mixed Signal ◽  
Device Architecture ◽  
Device Reliability ◽  
Process Architecture

AbstractIn a Mixed-Signal IC, both digital and analog circuits exist on the same chip. Analog circuit blocks require technology attributes like precise device matching, low parametric drifts and low noise. These requirements raise additional reliability issues, over and above the reliability concerns associated with digital circuits. CMOS device reliability for mixed-signal technologies can be enhanced by modifying device architecture and improving gate oxide integrity. Interconnect metallurgy plays an important role in determining electromigration related contact/via resistance change which may impact matching of devices and resistor pairs. Appropriate source/drain engineering, device design and utilizing nitrided gate oxide has been shown to produce extremely stable devices. This article will cover process architecture and material issues related with device stability and interconnect metallurgy issues related with contact/via stability, especially with W-Plugs.

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