Reliability Issues with Mixed-Signal CMOS Technology

1995 ◽  
Vol 391 ◽  
Author(s):  
Rajeeva Lahri ◽  
Hung-Sheng Chen ◽  
Ji Zhao ◽  
Kamesh Gadepally ◽  
C.S. Teng
Keyword(s):  
Analog Circuits ◽  
Analog Circuit ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Low Noise ◽  
Resistance Change ◽  
Mixed Signal ◽  
Device Architecture ◽  
Device Reliability ◽  
Process Architecture

AbstractIn a Mixed-Signal IC, both digital and analog circuits exist on the same chip. Analog circuit blocks require technology attributes like precise device matching, low parametric drifts and low noise. These requirements raise additional reliability issues, over and above the reliability concerns associated with digital circuits. CMOS device reliability for mixed-signal technologies can be enhanced by modifying device architecture and improving gate oxide integrity. Interconnect metallurgy plays an important role in determining electromigration related contact/via resistance change which may impact matching of devices and resistor pairs. Appropriate source/drain engineering, device design and utilizing nitrided gate oxide has been shown to produce extremely stable devices. This article will cover process architecture and material issues related with device stability and interconnect metallurgy issues related with contact/via stability, especially with W-Plugs.

Gate-Prior-To-Isolation Cmos-Technology with Through-The-Gate-Implanted Ultra-Thin Gate Oxides

1999 ◽  
Vol 567 ◽  
Author(s):  
Udo Schwalke ◽  
Christian Gruensfelder ◽  
Alexander Gschwandtner ◽  
Gudrun Innertsberger ◽  
Martin Kerber
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Wafer Surface ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Process Architecture ◽  
Process Complexity ◽  
Mos Gate ◽  
Cluster Tool

ABSTRACTWe have realized direct-tunneling gate oxide (1.6nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a comer parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in-situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench comer parasitics are eliminated by the advanced process architecture EXTIGATE without increasing process complexity.

scholarly journals FinFET Based Tunable Analog Circuit: Design and Analysis at 45 nm Technology

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
Ravindra Singh Kushwah ◽  
Shyam Akashe
Keyword(s):  
Analog Circuits ◽  
High Performance ◽  
Analog Circuit ◽  
Schmitt Trigger ◽  
Low Noise ◽  
Operational Transconductance Amplifier ◽  
Back Gate ◽  
Amplifier Circuit ◽  
Tunable Circuits ◽  
Transconductance Amplifier

We included a designing of low power tunable analog circuits built using independently driven FinFETs devices, where the controlling of the back gate provide the output on the front gate. We show that this could be an effective solution to conveniently tune the output of bulk CMOS analog circuits particularly for Schmitt trigger and operational transconductance amplifier circuits. FinFET devices can be used to increase the performance by reducing the leakage current and power dissipation, because front and back gates both are independently controlled. FinFET device has a higher controllability, resulting relatively high Ion/Ioff ratio. In this paper, we proposed a tunable analog circuit such as CMOS amplifier circuit, Schmitt trigger circuit, and operational transconductance amplifier circuit, these circuit blocks are necessary for low noise high performance ICs for analog applications. Gain, phase, group delay, and output response of analog tunable circuits have been discussed in this paper. The proposed FinFET based analog tunable circuits have been designed using Cadence Virtuoso tool at 45 nm.

scholarly journals CMOS Inverter as Analog Circuit: An Overview

2019 ◽  
Vol 9 (3) ◽  
pp. 26 ◽  
Author(s):  
Woorham Bae
Keyword(s):  
Analog Circuits ◽  
High Speed ◽  
Analog Circuit ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Cmos Inverter ◽  
Technology Scaling ◽  
Resistive Feedback ◽  
Output Driver

Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

scholarly journals Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 27
Author(s):  
Jingtian Liu ◽  
Qian Sun ◽  
Bin Liang ◽  
Jianjun Chen ◽  
Yaqing Chi ◽  
...  
Keyword(s):  
Circuit Design ◽  
Analog Circuits ◽  
Analog Circuit ◽  
Forward Bias ◽  
Cmos Technology ◽  
Common Source ◽  
Single Event ◽  
Single Event Transient ◽  
Body Effect ◽  
Radiation Hardened

In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.

ACHIEVING ANALOG ACCURACY IN NANOMETER CMOS

2005 ◽  
Vol 15 (02) ◽  
pp. 255-275 ◽  
Author(s):  
MICHAEL P. FLYNN ◽  
SUNGHYUN PARK ◽  
CHUN C. LEE
Keyword(s):  
Power Consumption ◽  
Analog Circuits ◽  
Thermal Noise ◽  
Analog Circuit ◽  
Cmos Technology ◽  
Mos Transistor ◽  
Nanometer Cmos ◽  
Transistor Mismatch ◽  
Current Design ◽  
Circuit Techniques

This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that VT matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

scholarly journals A low-noise current preamplifier in 120 nm CMOS technology

2008 ◽  
Vol 6 ◽  
pp. 213-217 ◽  
Author(s):  
H. Uhrmann ◽  
W. Gaberl ◽  
H. Zimmermann
Keyword(s):  
High Speed ◽  
Analog Circuit ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Special Focus ◽  
Current Mirror ◽  
Chip Area ◽  
The Impact

Abstract. In this paper we examine the impact of deep sub-micron CMOS technology on analog circuit design with a special focus on the noise performance and the ability to design low-noise preamplifiers. To point out, why CMOS technology can grow to a key technology in low-noise and high-speed applications, various amplifier stages, applied in literature, are compared. One, that fits as a current preamplifier for low-noise applications, is the current mirror. Starting from the basic current mirror, an enhanced current preamplifier is developed, that offers low-noise and high-speed operation. The suggested chip is realized in 0.12 μm CMOS technology and needs a chip area of 100 μm×280 μm. It consumes about 15 mW at a supply voltage of 1.5 V. The presented current preamplifier has a bandwidth of 750 MHz and a gain of 36 dB. The fields of application for current preamplifiers are, for instance, charge amplifiers, amplifiers for low-voltage differential signaling (LVDS) based point-to-point data links or preamplifiers for photodetectors.

Analog Circuit Failure Analysis Using Time-Resolved Emission

2005 ◽  
Author(s):  
B.J. Cain ◽  
G.L. Woods ◽  
A. Syed ◽  
R. Herlein ◽  
Toshihiro Nomura
Keyword(s):  
Analog Circuits ◽  
Integrated Circuit ◽  
Analog Circuit ◽  
Photon Emission ◽  
Nonlinear Process ◽  
Time Resolved ◽  
Non Invasive ◽  
Highly Nonlinear ◽  
Excellent Spatial Resolution ◽  
5 Ghz

Abstract Time-Resolved Emission (TRE) is a popular technique for non-invasive acquisition of time-domain waveforms from active nodes through the backside of an integrated circuit. [1] State-of-the art TRE systems offer high bandwidths (> 5 GHz), excellent spatial resolution (0.25um), and complete visibility of all nodes on the chip. TRE waveforms are typically used for detecting incorrect signal levels, race conditions, and/or timing faults with resolution of a few ps. However, extracting the exact voltage behavior from a TRE waveform is usually difficult because dynamic photon emission is a highly nonlinear process. This has limited the perceived utility of TRE in diagnosing analog circuits. In this paper, we demonstrate extraction of voltage waveforms in passing and failing conditions from a small-swing, differential logic circuit. The voltage waveforms obtained were crucial in corroborating a theory for some failures inside an 0.18um ASIC.

Laser Based Analysis on Analog Circuits with Feedback Loops and a Case Study

2006 ◽  
Author(s):  
Fubin Zhang ◽  
David Maxwell
Keyword(s):  
Success Rate ◽  
High Resistance ◽  
Analog Circuits ◽  
Analog Circuit ◽  
Feedback Loops ◽  
Induced Voltage ◽  
Analog Device ◽  
Analog Ic ◽  
Successful Isolation

Abstract Based on the understanding of laser based techniques’ physics theory and the topology/structure of analog circuit systems with feedback loops, the propagation of laser induced voltage/current alteration inside the analog IC is evaluated. A setup connection scheme is proposed to monitor this voltage/current alteration to achieve a better success rate in finding the fail site or defect. Finally, a case of successful isolation of a high resistance via on an analog device is presented.

Concepts for In Situ Diagnostics in Analog Microelectronic Circuits

2007 ◽  
Author(s):  
Ted Kolasa ◽  
Alfredo Mendoza
Keyword(s):  
Analog Circuits ◽  
System Architecture ◽  
Analog Circuit ◽  
Fault Localization ◽  
Diagnostic System ◽  
Diagnostic Capability ◽  
Common Signal ◽  
Diagnostic Capabilities ◽  
In Situ Diagnostics

Abstract Comprehensive in situ (designed-in) diagnostic capabilities have been incorporated into digital microelectronic systems for years, yet similar capabilities are not commonly incorporated into the design of analog microelectronics. And as feature sizes shrink and back end interconnect metallization becomes more complex, the need for effective diagnostics for analog circuits becomes ever more critical. This paper presents concepts for incorporating in situ diagnostic capability into analog circuit designs. Aspects of analog diagnostic system architecture are discussed as well as nodal measurement scenarios for common signal types. As microelectronic feature sizes continue to shrink, diagnostic capabilities such as those presented here will become essential to the process of fault localization in analog circuits.

60 GHz-Band Low-Noise Amplifier

2017 ◽  
Vol 26 (05) ◽  
pp. 1750075 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Zhi-Gong Wang ◽  
Muhammad Ovais Akhter ◽  
Muhammad Tariq Afridi
Keyword(s):  
Transmission Line ◽  
Quality Factor ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Constant Current ◽  
60 Ghz ◽  
Frequency Range ◽  
Constant Current Density ◽  
Chip Area

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.

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