A Comparison of Floating-Body Potential in H-Gate Ultrathin Gate Oxide Partially Depleted SOI pMOS and nMOS Devices Based on 90-nm SOI CMOS Process

2004 ◽  
Vol 25 (4) ◽  
pp. 214-216
Author(s):  
S.-S. Chen ◽  
S. Huang-Lu ◽  
T.-H. Tang
Keyword(s):  
Gate Oxide ◽  
Floating Body ◽  
Cmos Process ◽  
Body Potential ◽  
Soi Cmos

Gate Oxide Breakdown in a SOI CMOS Process Using MESA Isolation

ESSDERC ’89 ◽  
1989 ◽  
pp. 893-896 ◽  
Author(s):  
M. Haond ◽  
O. Le Neel ◽  
G. Mascarin ◽  
J. P. Gonchond
Keyword(s):  
Gate Oxide ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Soi Cmos

Gate oxide breakdown behaviour in a mesa SOI CMOS process

2003 ◽  
Author(s):  
M. Haond ◽  
O. Le Neel ◽  
G. Mascarin ◽  
J.P. Gonchond
Keyword(s):  
Gate Oxide ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Soi Cmos

Efficacy of Ar in reducing the kink effect on floating-body NFD/SOI CMOS

2002 ◽  
Author(s):  
D. Chang ◽  
S. Veeraraghavan ◽  
M. Mendicino ◽  
M. Rashed ◽  
D. Connelly ◽  
...  
Keyword(s):  
Floating Body ◽  
Kink Effect ◽  
Soi Cmos

scholarly journals Hot-carrier-induced degradation of drain current hysteresis and transients in thin gate oxide floating body partially depleted SOI nMOSFETs

2006 ◽  
Vol 46 (9-11) ◽  
pp. 1657-1663 ◽  
Author(s):  
J.M. Rafí ◽  
E. Simoen ◽  
K. Hayama ◽  
A. Mercha ◽  
F. Campabadal ◽  
...  
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Floating Body ◽  
Hot Carrier ◽  
Thin Gate Oxide

On the great potential of non-doped MOSFETs for analog applications in partially-depleted SOI CMOS process

2005 ◽  
Vol 49 (5) ◽  
pp. 708-715 ◽  
Author(s):  
V. Kilchytska ◽  
D. Levacq ◽  
L. Vancaillie ◽  
D. Flandre
Keyword(s):  
Cmos Process ◽  
Soi Cmos

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

45 GHz silicon MESFETs on a 0.15 µm SOI CMOS process

2009 ◽  
Author(s):  
W. Lepkowski ◽  
S.J. Wilk ◽  
T.J. Thornton
Keyword(s):  
Cmos Process ◽  
Soi Cmos
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