Commercially developed mixed-signal CMOS process features for application in advanced ROICs in 0.18μm technology node

2012 ◽  
Author(s):  
Arjun Kar-Roy ◽  
Paul Hurwitz ◽  
Richard Mann ◽  
Yasir Qamar ◽  
Samir Chaudhry ◽  
...  
Keyword(s):  
Cmos Process ◽  
Mixed Signal ◽  
Technology Node

A 3.2 mW Mixed-Signal Readout Circuit for an Organic Vertical Nano-Junctions Sensor

2016 ◽  
Author(s):  
Paul C.-P. Chao ◽  
Chin-I Su ◽  
Trong-Hieu Tran ◽  
Hsiao-Wen Zan
Keyword(s):  
Simple Structure ◽  
Low Cost ◽  
Time Response ◽  
Cmos Process ◽  
Readout Circuit ◽  
Readout System ◽  
Transient Time ◽  
Mixed Signal ◽  
Ammonia Detection ◽  
Signal Readout

A new sensitivity organic vertical nano-junctions (VNJ) sensor for ammonia detection and its readout system are presented in this study. The designed ammonia sensor, VNJP3HT diode, is a simple structure with real-time response, high reproducibility and low-cost sensor. Along with the designed sensor, a precision and robust readout circuit is designed and successfully implemented as the proposed chip in this study. To utilize for a novel organic bio-chip, a particular readout system is presented that can acquire signal, compute and display concentration values of ammonia without using microcontroller. The chip is fabricated by the TSMC 0.18-μm 1P6M 3.3V mixed-signal CMOS process technique for verification. Experiment results show that the average resolution is 70.48mV/log (ppm) in a short transient time response, 50 seconds, as compared to prior study, 200 seconds. Error rate, average noise and detection rate reliability are 2.86%, 123 μVrms, and 99.6%, respectively. This chip could be suitable for application in cars, cell phones, watches, etc.

2.4 GHz ISM-Band Receiver Design in a 0.18 $\mu{\hbox{m}}$ Mixed Signal CMOS Process

2007 ◽  
Vol 17 (10) ◽  
pp. 736-738 ◽  
Author(s):  
Hee-Sauk Jhon ◽  
Ickhyun Song ◽  
In Man Kang ◽  
Hyungcheol Shin
Keyword(s):  
Cmos Process ◽  
Receiver Design ◽  
Mixed Signal ◽  
Ism Band

scholarly journals A Mixed-Signal Programmable Time-Division Power-On-Reset and Volume Control Circuit for High-Resolution Hearing-Aid SoC Application

2018 ◽  
Vol 2018 ◽  
pp. 1-7
Author(s):  
Chengying Chen ◽  
Liming Chen ◽  
Jun Yang
Keyword(s):  
Low Power ◽  
Control Function ◽  
Hearing Aid ◽  
Sar Adc ◽  
Volume Control ◽  
Cmos Process ◽  
Mixed Signal ◽  
Analog To Digital ◽  
Power Application ◽  
Time Division

A mixed-signal programmable Time-Division Power-On-Reset (TD-POR) circuit based on 8-bit Successive Approximation Analog-to-Digital Converter (SAR ADC) for accurate control in low-power hearing-aid System on Chip (SoC) is presented in this paper. The end-of-converter (EOC) signal of SAR ADC is used as the mode-change signal so that the circuit can detect the battery voltage and volume voltage alternately. And the TD-POR circuit also has brown-out reset (BOR) detection capability. Through digital logic circuit, the POR, BOR threshold, and delay time can be adjusted according to the system requirement. The circuit is implemented in SMIC 0.13 μm 1P8M CMOS process. The measurement results show that, in 1 V power supply, the POR, BOR, and volume control function are accomplished. The detection resolution is the best among previous work. With 120 Hz input signal and 15 kHz clock, the ADC shows that Signal to Noise plus Distortion Ratio (SNDR) is 46.5 dB and Effective Number Of Bits (ENOB) is 7.43 bits. Total circuit power consumption is only 86 μw for low-power application.

A 1V, 1.1mW mixed-signal hearing aid SoC in 0.13μm CMOS process

2016 ◽  
Author(s):  
Chengying Chen ◽  
Liming Chen ◽  
Jun Fan ◽  
Zenghui Yu ◽  
Jun Yang ◽  
...  
Keyword(s):  
Hearing Aid ◽  
Cmos Process ◽  
Mixed Signal

scholarly journals MOS capacitances used in mixed-signal circuits and their operative range

2003 ◽  
Vol 1 ◽  
pp. 295-299 ◽  
Author(s):  
W. Kraus ◽  
B. Stelzig ◽  
T. Tille ◽  
D. Schmitt-Landsiedel
Keyword(s):  
Low Voltage ◽  
Cmos Process ◽  
Mixed Signal ◽  
High Linearity ◽  
Mixed Signal Circuits ◽  
The Right ◽  
The Impact

Abstract. To avoid additional layers for high linearity capacitances in modern CMOS process families, compensated depletion mode MOS capacitances can be used. As shown in previous publications, these MOS capacitances are suitable for low voltage applications. But there exist limitations concerning the linearity of these capacitances. In this work, the impact of the nonlinearity of the capacitances on different kinds of circuits is investigated. Several examples will be discussed to show how to choose the right capacitance topology.

A Mixed Signal DC Offset Cancellation for VGA of Zero-IF Receiver

2016 ◽  
Vol 26 (03) ◽  
pp. 1750047
Author(s):  
Yiqiang Zhao ◽  
Jingshuai Wang ◽  
Yun Sheng
Keyword(s):  
Calibration Method ◽  
Compensation Voltage ◽  
Digital Logic ◽  
Cmos Process ◽  
Mixed Signal ◽  
Offset Cancellation ◽  
Dc Offset ◽  
Measurement Results ◽  
Calibration Time

This paper proposes a mixed signal DC offset cancellation (DCOC) which does not cause the near-DC rejection for zero-IF receiver. To achieve low output offset efficiently, the DCOC consisting of a comparator, a digital logic controller and compensation voltage generators is used. It utilizes current sources arrays that are controlled by thermometer code to generate the compensation voltage. The proposed DCOC is implemented in GF 0.18 [Formula: see text]m CMOS process. The measurement results show that the proposed calibration method can reduce the offset residue to less than 80 mV and the total calibration time is less than 13 [Formula: see text]s. It only drains 60 [Formula: see text]A from a 3.3 V supply.

scholarly journals Ein 10 bit 10MS/s Low-Power AD-Converter in 0.11mm2

2005 ◽  
Vol 2 ◽  
pp. 205-209
Author(s):  
D. Muthers ◽  
R. Tielert
Keyword(s):  
Low Power ◽  
Small Area ◽  
Digital Filters ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Mixed Signal ◽  
Analog To Digital ◽  
Ad Converter ◽  
Mim Capacitors

Abstract. Ein 10 bit 10MS/s Analog-Digital- Wandler mit niedriger Leistungaufnahme von 8,4mW wurde implementiert. Der geringe Flächenbedarf von 0,11mm2 macht diesen Wandler besonders geeignet f¨ur Multikanalanwendungen. Um die Anforderungen von 10 bit, 10 MS/s möglichst effizient zu erfüllen wurde eine zyklische Wandlerarchitektur gewählt, die in einem 0,18μm-CMOSProzess mit MIM-Kondensatoren implementiert wurde. Der entworfene ADC wurde in 21 parallelen Kanälen auf einem mixed-signal-Chip zusammen mit digitalen Filtern, vier RISC-CPUs und I/O-Schaltungen implementiert. A 10 bit 10MS/s Analog to Digital Converter, consuming a power of 8,4mW, has been implemented. Due to the small area of 0,11mm2 this ADC is highly suited for multichannel implementations. A cyclic converter architecture is best suited for this application, being implemented in a 0,18μm CMOS process with MIM-capacitors. The designed ADC was implemented in an array of 21 channels on a mixed signal chip together with digital filters, four RISC-CPUs and I/O circuitry.

scholarly journals Performance Optimization and Comparison of CNT Interconnect with Copper at VDSM Technology

2013 ◽  
Vol 6 (2) ◽  
pp. 826-834
Author(s):  
Kureshi Abdul Kadir ◽  
Mohd Hasan
Keyword(s):  
Carbon Nanotube ◽  
Performance Optimization ◽  
Energy Efficient ◽  
Deep Submicron ◽  
Copper Interconnects ◽  
Cmos Process ◽  
Process Technology ◽  
Technology Node ◽  
Global Interconnects ◽  
Cu Interconnect

As the CMOS process technology continues to scale, standard copper (Cu) interconnect will become a major hurdle for the best performance at very deep submicron (VDSM) technology node. The carbon nanotube (CNT) bundles have potential to provide an attractive solution for the higher resistivity and electromigration problems faced by traditional copper interconnects in VDSM technology node. This paper presents important guidelines to minimize the resistance, capacitance and inductance of a mixed CNT bundle interconnect for achieving best performance. The performance of mixed CNT bundle and copper is then compared at local and global interconnects level at 22nm technology node. HSPICE simulations carried out using Berkeley predictive technology model (BPTM) at an operating frequency of 1GHz, shows that for interconnect length of 1000um, the mixed CNT and optimized CNT (CNT_Opt) bundles are 1.98X and 2.20X faster, 74% and 84% more energy efficient respectively than the Copper interconnects.

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