SIP with TSV for Class 1 Medical Devices

2014 ◽  
Vol 2014 (1) ◽  
pp. 000313-000318
Author(s):  
Doug Link
Keyword(s):  
Flip Chip ◽  
Hearing Aid ◽  
Form Factors ◽  
Multichip Module ◽  
Back Side ◽  
Passive Components ◽  
Wire Bonds ◽  
Electrical Interconnection ◽  
Hearing Instruments ◽  
Class 1

The demand for greater performance of hearing instruments in smaller form factors continues to drive the need for miniaturization of microelectronic packages. Reported here is how TSV technology was used to shrink the size of a conventional DSP-based system in package (SIP) used in the smallest In-The-Ear (ITE) hearing instruments. The conventional SIP is a heterogeneous multichip module containing a wire bonded EEPROM die mounted atop a DSP flip chip die along with 10 passive components built upon a high density alumina substrate. The wire bonds of the conventional SIP, along with the extra space they require, are eliminated and replaced by TSV structures fabricated in the DSP IC wafer using the via last method. A redistribution layer on the back side of the DSP IC enables direct attachment and electrical interconnection of the memory IC to the DSP IC. The result is a 23% smaller SIP with functionality demonstrated in hearing aid prototypes. This is believed to be the first demonstration of TSV in a heterogeneous hearing aid multichip module. This paper describes the design approach, materials, basic process steps, results, and challenges encountered in creating this novel TSV-SIP.

SIP with TSV for Class 1 Medical Devices

2016 ◽  
Vol 13 (1) ◽  
pp. 1-5 ◽  
Author(s):  
Youngtak Lee ◽  
Doug Link
Keyword(s):  
Integrated Circuit ◽  
Flip Chip ◽  
Hearing Aid ◽  
Form Factors ◽  
Digital Signal ◽  
Multichip Module ◽  
Back Side ◽  
Digital Signal Process ◽  
Hearing Instruments ◽  
Class 1

The demand for greater performance of hearing instruments in smaller form factors continues to drive the need for miniaturization of microelectronic packages. This article reports how through-silicon-via (TSV) technology was used to shrink the size of a conventional digital signal process (DSP)-based system in package (SIP) used in the smallest in-the-ear hearing instruments. The conventional SIP is a heterogeneous multichip module containing a wire-bonded electrically erasable programmable read-only memory (EEPROM) die mounted atop a DSP flip-chip die along with 10 passive components built upon a high-density alumina substrate. The wire bonds of the conventional SIP, along with the extra space they require, are eliminated and replaced by TSV structures fabricated in the DSP integrated circuit (IC) wafer using the via-last method. A redistribution layer on the back side of the DSP IC enables direct attachment and electrical interconnection of the memory IC to the DSP IC. The result is a 23% smaller SIP with functionality demonstrated in hearing aid prototypes. This is believed to be the first demonstration of TSV in a heterogeneous hearing aid multichip module. This article describes the design approaches, materials, basic process steps, results, and challenges encountered in creating this novel TSV-SIP.

Multi-Stacked Flip Chips with Copper Plated Through Silicon Vias and Re-distribution for 3D System-in-Package Integration

2006 ◽  
Vol 970 ◽  
Author(s):  
Shi-Wei Ricky Lee ◽  
Ronald Hon
Keyword(s):  
Flip Chip ◽  
Three Dimensional ◽  
Back Side ◽  
Wafer Level ◽  
Flip Chips ◽  
Electrical Interconnection ◽  
Solder Balls ◽  
Original Size ◽  
Structure Lead ◽  
Silicon Vias

ABSTRACTThe study is a prototype design and fabrication of multi-stacked flip chip three dimensional packaging (3DP) with TSVs for interconnection. Three chips are stacked together to make a 3DP with solder bumped flip chips. TSVs are fabricated and distributed along the periphery of the middle chip. The TSVs are formed by dry etching, deep reactive ions etching (DRIE), with dimensions of 150 × 100 microns. The TSVs are plugged by copper plating. The filled TSVs are connected to the solder pads by extended pad patterns surrounding the top and the bottom of TSVs on both sides of the wafer for the middle chip. After pad patterning passivation and solder bumping, the wafer is sawed into chips for subsequent 3D stacked die assembly. Because the TSVs are located at the periphery of the middle chips and stretch across the saw street between adjacent chips, they will be sawed through their center to form two open TSVs (with half of the original size) for electrical interconnection between the front side and the back side of the middle chip. The top chip is made by the conventional solder bumped flip chip processes and the bottom chip is a carrier with some routing patterns. The three middle chips and top chip are stacked by a flip chip bonder and the solder balls are reflowed to form the 3DP structure. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented.

On the Way from Fan-out Wafer to Fan-out Panel Level Packaging

2016 ◽  
Vol 2016 (S2) ◽  
pp. S1-S23 ◽  
Author(s):  
Karl-Friedrich Becker ◽  
Tanja Braun ◽  
S. Raatz ◽  
M. Minkus ◽  
V. Bader ◽  
...  
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Layer Structure ◽  
Form Factors ◽  
Circuit Board ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Bga Packages ◽  
Wire Bonds ◽  
Near Future

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Manufacturing is currently done on wafer level up to 12″/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are forecasted for the near future. Instead of following the wafer level approach to 450 mm, panel level packaging will be the next big step. Sizes for the panel could range up to 18″×24″ or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. An overview of state of technology for panel level packaging will be presented and discussed in detailed.

3D Wire Bondless Integration: The Future of Silicon Carbide (SiC) Packaging

2017 ◽  
Author(s):  
Sayan Seal ◽  
Andrea K. Wallace ◽  
John E. Zumbro ◽  
H. Alan Mantooth
Keyword(s):  
Electromagnetic Interference ◽  
Flip Chip ◽  
Wide Bandgap ◽  
Switching Losses ◽  
Wire Bonds ◽  
Electrical Interconnection ◽  
Power Modules ◽  
Chip Scale Package ◽  
Solder Balls ◽  
High Temperature Operation

Wide bandgap (WBG) semiconductors are revolutionizing the world of power electronics. They have the potential to bring about an unprecedented increase in power density. The ability to switch at ultrafast rates, coupled with the promise of high temperature operation, make these devices extremely desirable. However, having superior semiconductor devices will not automatically translate to superior package characteristics. In real applications, the performance of a power device is only as good as the package allows. One of the major drawbacks plaguing contemporary power modules is the wire-bonded interconnection. Wire bonds offer a high parasitic inductance. This paper presents a novel wire bondless SiC power MOSFET packaging technique. A commercially available bare die was reconfigured into a chip-scale package. The new form factor enabled the MOSFET to be bonded to a patterned FR4 substrate using flip-chip bonding. The electrical interconnection between the package and the substrate was established using solder balls — thus eliminating the requirement for wire bonds. The motivation for using a wire bondless method was a reduction in stray parasitic inductances and an increase in the thermo-mechanical reliability. Lower parasitic inductances will facilitate high switching frequencies which will promote miniaturization, a reduction in electromagnetic interference (EMI), and lead to lower switching losses. The proposed approach was demonstrated to reduce the parasitic loop inductance by a fctor of > 3× as compared with wire bonded modules.

Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology

2010 ◽  
Author(s):  
K. Dickson ◽  
G. Lange ◽  
K. Erington ◽  
J. Ybarra
Keyword(s):  
Electron Beam ◽  
Flip Chip ◽  
Back Side ◽  
Soi Technology

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.

The Effects of Receiver Placement on Probe Microphone, Performance, and Subjective Measures with Open Canal Hearing Instruments

2010 ◽  
Vol 21 (04) ◽  
pp. 249-266 ◽  
Author(s):  
Lynzee N. Alworth ◽  
Patrick N. Plyler ◽  
Monika Bertges Reber ◽  
Patti M. Johnstone
Keyword(s):  
Repeated Measures ◽  
Hearing Aid ◽  
Clinical Importance ◽  
Ease Of Use ◽  
Subjective Measures ◽  
Repeated Measures Design ◽  
Hearing Instruments ◽  
Data Collection And Analysis ◽  
Significant Difference ◽  
Occlusion Effect

Background: Open canal hearing instruments differ in method of sound delivery to the ear canal, distance between the microphone and the receiver, and physical size of the devices. Moreover, RITA (receiver in the aid) and RITE (receiver in the ear) hearing instruments may also differ in terms of retention and comfort as well as ease of use and care for certain individuals. What remains unclear, however, is if any or all of the abovementioned factors contribute to hearing aid outcome. Purpose: To determine the effect of receiver location on performance and/or preference of listeners using open canal hearing instruments. Research Design: An experimental study in which subjects were exposed to a repeated measures design. Study Sample: Twenty-five adult listeners with mild sloping to moderately severe sensorineural hearing loss (mean age 67 yr). Data Collection and Analysis: Participants completed two six-week trial periods for each device type. Probe microphone, objective, and subjective measures (quiet, noise) were conducted unaided and aided at the end of each trial period. Results: Occlusion effect results were not significantly different between the RITA and RITE instruments; however, frequency range was extended in the RITE instruments, resulting in significantly greater maximum gain for the RITE instruments than the RITA instruments at 4000 and 6000 Hz. Objective performance in quiet or in noise was unaffected by receiver location. Subjective measures revealed significantly greater satisfaction ratings for the RITE than for the RITA instruments. Similarly, preference in quiet and overall preference were significantly greater for the RITE than for the RITA instruments. Conclusions: Although no occlusion differences were noted between instruments, the RITE did demonstrate a significant difference in reserve gain before feedback at 4000 and 6000 Hz. Objectively; no positive benefit was noted between unaided and aided conditions on speech recognition tests. These results suggest that such testing may not be sensitive enough to determine aided benefit with open canal instruments. However, the subjective measures (Abbreviated Profile of Hearing Aid Benefit [APHAB] and subjective ratings) did indicate aided benefit for both instruments when compared to unaided. This further suggests the clinical importance of subjective measures as a way to measure aided benefit of open-fit devices.

Evaluation of Low Stress Photo-Sensitive Spin On Dielectric Layers for Through Silicon Via (TSV) Copper Redistribution Layers

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000666-000698
Author(s):  
Christopher Jahnes ◽  
Eric Huenger ◽  
Scott Kisting
Keyword(s):  
Power Distribution ◽  
Flip Chip ◽  
Dielectric Materials ◽  
Back Side ◽  
Thermal Reliability ◽  
Dielectric Layers ◽  
Chip Size ◽  
Package Density ◽  
Silicon Vias ◽  
Wafer Thinning

To increase performance of semiconductor devices advances in packaging such as chip stacking (3D) and silicon carrier technologies (SoC) are being developed. Adaptation of these packaging fabrication methods offers the ability to incorporate functionality as well as provide memory and power distribution on one IC with increased signal bandwidth. An enabling element in both the stacking and silicon carrier technologies is through silicon vias (TSV) which electrically connect dies to a silicon carrier or via stacked chips (1). Creation of TSV involves via fabrication, wafer thinning and back side wafer finishing, to name a few, some of which are relatively new to semiconductor processing. Furthermore, because the wafer backside is accessible it can now be utilized to route wiring to further increase package density. The focus of this research was to evaluate photo-sensitive spin on dielectric materials (SOD) that can be used as the backside wiring levels, commonly referred to as redistribution layers (RDL) in TSV technologies. The two materials evaluated are; the epoxy based Dow INTERVIA™ 8023 Dielectric and the Benzocyclobutene (BCB) polymer, Dow CYCLOTENE™ 4000 product series. These dielectric materials have low stress and provide good planarization (2). Test vehicles with a chip size of 3.7 cm x 2.26 cm were fabricated with a 6 um wide copper RDL layer using the SOD materials of interest as well as conventional PECVD SiO2/SiN dielectric layers. The large chip size accommodated parallel Cu lines running 1.8 cm long with a spacing of 3 m and represented an aggressive shorting test for the SOD materials. It also enhances chip distortion after thinning and is evaluated for all three test vehicles. Chips were then electrically tested through simulated 260° C reflow cycles (for flip chip joining) and accelerated thermal reliability tests from −55° C to 125° C for 1000 cycles.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000325-000332 ◽  
Author(s):  
Alan Huffman ◽  
Philip Garrou
Keyword(s):  
Technological Change ◽  
Flip Chip ◽  
Emerging Technologies ◽  
Unit Area ◽  
Form Factors ◽  
Electrical Performance ◽  
Wafer Level ◽  
3D Integration ◽  
Wafer Level Packaging ◽  
Area Array

As IC scaling continues to shrink transistors, the increased number of circuits per chip requires more I/O per unit area (Rent's rule). High I/O count, the need for smaller form factors and the need for better electrical performance drove the technological change towards die being interconnected (assembled) by area array techniques. This review will examine this evolution from die wire bonded on lead frames to flip chip die in wafer level or area array packages and discuss emerging technologies such as copper pillar bumps, fan out packaging, integrated passives, and 3D integration..

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