Thermal effect on die warpage during back-side die polishing of flip-chip BGA device

2013 ◽  
Author(s):  
M. Mezanur Rahman Monjur ◽  
M.S. Wei ◽  
H.B. Chong ◽  
L Nasar-Abdat ◽  
Vinod Narang
Keyword(s):  
Thermal Effect ◽  
Flip Chip ◽  
Back Side

Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology

2010 ◽  
Author(s):  
K. Dickson ◽  
G. Lange ◽  
K. Erington ◽  
J. Ybarra
Keyword(s):  
Electron Beam ◽  
Flip Chip ◽  
Back Side ◽  
Soi Technology

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.

Evaluation of Low Stress Photo-Sensitive Spin On Dielectric Layers for Through Silicon Via (TSV) Copper Redistribution Layers

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000666-000698
Author(s):  
Christopher Jahnes ◽  
Eric Huenger ◽  
Scott Kisting
Keyword(s):  
Power Distribution ◽  
Flip Chip ◽  
Dielectric Materials ◽  
Back Side ◽  
Thermal Reliability ◽  
Dielectric Layers ◽  
Chip Size ◽  
Package Density ◽  
Silicon Vias ◽  
Wafer Thinning

To increase performance of semiconductor devices advances in packaging such as chip stacking (3D) and silicon carrier technologies (SoC) are being developed. Adaptation of these packaging fabrication methods offers the ability to incorporate functionality as well as provide memory and power distribution on one IC with increased signal bandwidth. An enabling element in both the stacking and silicon carrier technologies is through silicon vias (TSV) which electrically connect dies to a silicon carrier or via stacked chips (1). Creation of TSV involves via fabrication, wafer thinning and back side wafer finishing, to name a few, some of which are relatively new to semiconductor processing. Furthermore, because the wafer backside is accessible it can now be utilized to route wiring to further increase package density. The focus of this research was to evaluate photo-sensitive spin on dielectric materials (SOD) that can be used as the backside wiring levels, commonly referred to as redistribution layers (RDL) in TSV technologies. The two materials evaluated are; the epoxy based Dow INTERVIA™ 8023 Dielectric and the Benzocyclobutene (BCB) polymer, Dow CYCLOTENE™ 4000 product series. These dielectric materials have low stress and provide good planarization (2). Test vehicles with a chip size of 3.7 cm x 2.26 cm were fabricated with a 6 um wide copper RDL layer using the SOD materials of interest as well as conventional PECVD SiO2/SiN dielectric layers. The large chip size accommodated parallel Cu lines running 1.8 cm long with a spacing of 3 m and represented an aggressive shorting test for the SOD materials. It also enhances chip distortion after thinning and is evaluated for all three test vehicles. Chips were then electrically tested through simulated 260° C reflow cycles (for flip chip joining) and accelerated thermal reliability tests from −55° C to 125° C for 1000 cycles.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

Development of Organic Multi Chip Package for High Performance Application

2013 ◽  
Vol 2013 (1) ◽  
pp. 000414-000414 ◽  
Author(s):  
Noriyoshi Shimizu ◽  
Wataru Kaneda ◽  
Hiromu Arisaka ◽  
Naoyuki Koizumi ◽  
Satoshi Sunohara ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Metal Layer ◽  
Small Diameter ◽  
Organic Substrate ◽  
Back Side ◽  
Test Results ◽  
Manufacturing Method ◽  
Separate Step ◽  
High Performance Application

In recent years, it has become apparent that the conventional FC-BGA (Flip Chip Ball Grid Array) substrate manufacturing method (Electroless Cu plating, Desmear, Laser Drilling processing) is reaching its limits for finer wiring dimensions and narrower pitches of the flip chip pad. On the other hand, the demand for miniaturization and higher density continues to increase. Our solution is the Organic Multi Chip Package, a combined organic interposer and organic substrate. Unlike a conventional 2.5D interposer that is separately manufactured and then attached to a substrate PWB (Printed Wire Board), the interposer of our Organic Multi Chip Package is built directly onto an organic substrate. First normal build-up layers are laminated on both sides of the PWB core and metal traces formed by conventional semi-additive techniques. After the back side is coated with a typical SR layer for FC-BGA, the top surface and its laser-drilled vias are smoothed by CMP (Chemical Mechanical Polishing). A thin-film process is used to deposit the interposer's insulating resin layers. Then normal processes are applied to open small diameter vias and a metal seed layer is sputtered on. The wiring is patterned, and the metal traces are fully formed by plating. Finally, the Cu pads on the top layer are treated by OSP (Organic Solderability Preservative). In this paper we discuss results using a prototype 40 mm × 40 mm Organic Multi Chip Package. The prototype's organic substrate has a two-metal layer core with 100 μm diameter through-holes, two build-up layers on the chip side, and three plus a solder resist layer on the BGA side. The interposer has four wiring layers. Thus the structure of the prototype is 4+(2/2/3). For evaluation purposes, there are four patterns of lines and spaces on the interposer: 2 μm/2 μm, 3 μm/3 μm, 4 μm/4 μm, and 5 μm/5 μm. The metal trace thicknesses are 2.5 μm, via diameters are 10 μm, pad pitches are 40 μm, and the Cu pad diameters are 25 μm. These dimensions allow the Organic Multi Chip Package to easily make the pitch conversions of the IC to the PCB. With a 4+(2/2/3) structure, the Organic Multi Chip Package is asymmetric, raising concerns about package warping. However, the warping can be reduced by the optimization of structure and materials. In this way, we were able to connect a high pin-count logic chip to standard Wide I/O memory chips. We think that there are at least two obvious advantages of the Organic Multi Chip Package. The first is a total height reduction compared to a structure with a separate silicon interposer attached to a PWB substrate. The Organic Multi Chip Package, with its built-on interposer, eliminates the need for solder joints between the interposer and substrate. In addition, the fine resin layers make our interposer much thinner than a silicon interposer. The second advantage is simpler assembly. Our structure does not require the separate step of assembling an interposer to the substrate. Assembly costs should be lower and yields higher. In this paper we demonstrate the successful attainment of fine lines and spaces on the Organic Multi Chip Package. We also show and discuss reliability test results.

FUNDAMENTALS OF THE SQUEEZE-FLOW BETWEEN A HEAT SINK AND A FLIP-CHIP

2008 ◽  
Vol 32 (3-4) ◽  
pp. 467-486 ◽  
Author(s):  
M.A. Marois ◽  
M. Lacroix
Keyword(s):  
Heat Sink ◽  
Flip Chip ◽  
String Model ◽  
Thermal Interface Material ◽  
Squeeze Flow ◽  
Back Side ◽  
Two Dimensional ◽  
Particle Volume ◽  
Volume Fractions ◽  
Drop Flow

The paper presents the fundamentals of the squeeze-flow of the thermal interface material (TIM) that takes place during the pressing of a heat sink to the back side of a flip-chip is studied. A two-dimensional string model is developed for predicting the time-varying plate separation and squeeze-rate in terms of the squeeze force. The predictions are compared to a one-dimensional string model and to a squeeze-drop flow model. Results indicate that the flow resulting from the squeezing of a string of TIM between two rigid plates is truly two-dimensional. The effect of surface tension and of the heat transfer is found to be negligible under the assembly conditions. The flow behaviour of the TIM with suspensions of high thermal conductivity particles is also investigated. It is shown that the fluid remains Newtonian for particle volume fractions smaller than 30%. For volume fractions larger than 30%, the fluid becomes Non-Newtonian during the early stages of the squeezing process, i.e. for t ≤ 1s. In the later stages however (t > 10s), the fluid may be considered Newtonian.

FIB Micro-Surgery on Flip-Chips from the Backside

1998 ◽  
Author(s):  
Raymond Lee ◽  
Nicholas Antoniou
Keyword(s):  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Back Side ◽  
Bulk Silicon ◽  
Front Side ◽  
Large Hole ◽  
Area Of Interest ◽  
Flip Chip Packaging ◽  
Micro Surgery

Abstract The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness of tradhional micro-surgery. Advancements in FIB technology and its application now allow access to the circuitry from the backside through the bulk silicon. In order to overcome the problem of imaging through thick silicon, a microscope with Infra Red (IR) capability has been integrated into the FIB system. Navigation can now be achieved using the IR microscope in conjunction with CAD. The integration of a laser interferometer stage enables blind navigation and milling with sub-micron accuracy. To optimize the process, some sample preparation is recommended. Thinning the sample to a thickness of about 100 µm to 200 µm is ideal. Once the sample is thinned, it is then dated in the FIB and the area of interest is identified using the IR microscope. A large hole is milled using the FIB to remove most of the silicon covering the area of interest. At this point the application is very similar to more traditional FIB usage since there is a small amount of silicon to be removed in order to expose a node, cut it or reconnect it. The main differences from front-side applications are that the material being milled is conductive silicon (instead of dielectric) and its feature-less and therefore invisible to a scanned ion beam. In this paper we discuss in detail the method of back-side micro-surgery and its eflkcton device performance. Failure Analysis (FA) is another area that has been severely limited by flip-chip packaging. Localized thinning of the bulk silicon using FIB technology oflkrs access to diagnosing fdures in flip-chip assembled parts.

Groove Geometry and Mold Shrinkage Effects on Die Stress in Flip Chip Molded BGAs (FCMBGA)

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000455-000470
Author(s):  
Bora Baloglu ◽  
Miguel Jimarez ◽  
Ahmer Syed
Keyword(s):  
Finite Element ◽  
Finite Element Model ◽  
Flip Chip ◽  
Element Model ◽  
Shear Stresses ◽  
Back Side ◽  
Molding Process ◽  
Finite Elements Analysis ◽  
Design Guideline ◽  
Structural Support

Exposed die flip chip molded BGA (FCMBGA) packages are preferred for their improved thermal performance and reduced system cost. In this package type, mold compound replaces the traditional capillary underfill and also provides a better stiffening option for the package without the need for additional structural support such as lid and/or stiffening ring. In addition, it allows better utilization of the board real estate as the passive components can be placed closer to the die. Groove or an undercut is the shape of the mold around the exposed die that is formed during the molding process. To ensure a mold-free top surface of the die, a seal (soft insert) that has a larger surface area than the die is being used to cover the die top surface. This larger portion of the seal outlines the groove geometry when it is compressed on top of the die. Seal size can be designed to establish certain groove geometry. Thus, it is important to characterize/understand the effects of the groove geometry as it is a design parameter and can be adjusted to create more robust molded packages. In this study, specific groove width and depth values for various package configurations are investigated using finite elements analysis, FEA. Initially, a detailed finite element model is prepared and warpage simulation is performed. Model correlation to the actual Shadow Moiré is obtained. Then, using the correlated finite element model, die back side stress and shear stresses, where die faces mold compound, are obtained for a thermal cool down simulation from the molding temperature. Mold compound shrinkage is also considered by using an adjusted thermal expansion coefficient value. As a validation study, a test mold chase/tool for varying insert sizes has been designed and, molded packages with different groove geometries and different mold compounds were build. Using the correlation between the test data and the simulation results an order of importance (based on the groove geometry parameters and mold compound's material properties) will be presented which then, can be used as a design guideline to change the groove geometry to produce more robust molded packages.

Development of a stress compensation layer for thin pixel modules 3D assembly

2014 ◽  
Vol 2014 (1) ◽  
pp. 000787-000793 ◽  
Author(s):  
G. Pares ◽  
T. McMullen ◽  
S. Tomé ◽  
L. Vignoud ◽  
R. Bates ◽  
...  
Keyword(s):  
Room Temperature ◽  
Flip Chip ◽  
Building Blocks ◽  
Back Side ◽  
Pixel Detector ◽  
Front Side ◽  
Radiation Length ◽  
Reflow Temperature ◽  
Solder Reflow ◽  
Deposition Conditions

The pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in CERN LHC facility. They consist in their basic form of a silicon sensor that is flip-chipped bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach towards low mass modules and thus reducing radiation length. From the module perspective this can be achieved by using advanced 3D technology processes that includes the formation of copper and solder micro-bumps on top of the ROIC front-side, the thinning of both the sensor and the CMOS ROIC and finally the flip chip assembly of the 2 chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage due to bad co-planarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100um, the chip bow varies from − 100 μm at room temperature to + 175 μm at reflow temperature resulting of CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective is to compensate dynamically the stress of the front side stack by adding a compensating layer to the back-side of the wafer. Utilising our material thermo-mechanical database coupled with a proprietary analytical simulator and measuring the bow of the ROIC at die level we are able to reduce the bow magnitude by approximately a factor of 3 by the introduction of the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. This amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the backside deposition conditions are on-going where the target is to control the room temperature bow close to zero and reducing the bow magnitude throughout the full solder reflow temperature range hence conserving bump yield. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach in mind should we integrate this technology in the future.

Development of a Stress Compensation Layer for 3-D Assembly of Thin Pixel Modules

2015 ◽  
Vol 12 (1) ◽  
pp. 29-36
Author(s):  
G. Pares ◽  
T. McMullen ◽  
S. Tomé ◽  
L. Vignoud ◽  
R. Bates ◽  
...  
Keyword(s):  
Room Temperature ◽  
Flip Chip ◽  
Building Blocks ◽  
Back Side ◽  
Pixel Detector ◽  
Front Side ◽  
Radiation Length ◽  
Reflow Temperature ◽  
Solder Reflow ◽  
Deposition Conditions

Pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in the CERN LHC facility. In their basic form, they consist of a silicon sensor that is flip-chip bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach toward low-mass modules, thus reducing radiation length. From the module perspective, this can be achieved by using advanced 3-D technology processes that include the formation of copper and solder microbumps on top of the ROIC front side, the thinning of both the sensor and the CMOS ROIC, and, finally, the flip-chip assembly of the two chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage, due to bad coplanarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100 μm, the chip bow varies from −100 μm at room temperature to +175 μm at reflow temperature, resulting in CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective was to compensate dynamically for the stress of the front-side stack by adding a compensating layer to the back side of the wafer. Using our material thermomechanical database coupled with a proprietary analytical simulator, and measuring the bow of the ROIC at die level, we were able to reduce the bow magnitude by approximately a factor of 3 by introducing the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. The amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the back-side deposition conditions are ongoing, where the target is to control the room temperature bow close to zero and reduce the bow magnitude throughout the full solder reflow temperature range, hence conserving bump yield. In keeping with a 3-D process, the materials used are compatible with through-silicon via (TSV) technology with a TSV-last approach in mind, should we integrate this technology in the future.

LTCC-Based Highly Integrated SiPM Module with Integrated Liquid Cooling Channels for High Resolution Molecular Imaging

2018 ◽  
Vol 15 (2) ◽  
pp. 86-94 ◽  
Author(s):  
Rainer Dohle ◽  
Ilaria Sacco ◽  
Thomas Rittweg ◽  
Thomas Friedrich ◽  
Gerold Henning ◽  
...  
Keyword(s):  
Magnetic Resonance ◽  
Image Quality ◽  
Low Temperature ◽  
Flip Chip ◽  
Back Side ◽  
Liquid Cooling ◽  
Cooling Channels ◽  
Hybrid Detection ◽  
The Impact ◽  
Ltcc Substrate

We present a very compact hybrid detection module based on an advanced liquid-cooled low temperature cofired ceramic (LTCC) substrate. The double sided hybrid combines 144 photo detectors and four specialized flip chip readout ASICs (Application specific Integrated Circuits) used for the readout of scintillation crystals with application in time-of-flight positron emission tomography (PET) combined with magnetic resonance imaging (MRI). If MRI images and PET images are combined, completely new medical diagnostic and treatment prospects are feasible because the two techniques are complementary and they will offer both anatomical and functional information. One of the biggest challenges is the development of miniaturized detector modules that are highly functional and MRI compatible. Our SiPM (Silicon Photomultiplier) module has an area of 32.8 by 32.0 mm2 and contains 12 × 12 SiPMs in a pitch of 2.5 mm2. The SiPM readout of the 144 channels is performed by four PETA6 ASICs. The LTCC substrate with a 2.1 mm thickness has been manufactured using the most advanced technologies developed at Micro Systems Engineering GmbH To guarantee the manufacturability in serial or mass production, DP951 P2 green tape has been used. For the cooling channels, special technology has been developed by MSE. The liquid cooling channels inside the LTCC substrate provide excellent cooling for the ASICs, the SiPMs, and thermal insulation between ASICs and SiPMs and allow a very compact design of the detector modules, reducing their height by 50% compared with other technical solutions. We can insert a ring of our modules in an existing MR (Magnetic Resonance) scanner. Operating the SiPMs at low temperature improves their performance, reducing the effects of dark count rate and improving image quality. There is no heatsink, heat pipe, or other cooling element attached to the back side of the ASICs. To avoid interference between the PET and MRI system, short signal length is required for minimizing pickup loops and eddy currents. The 12 SiPM arrays with 2 × 6 geometry are wire bonded only at the edges of the SiPMs to the LTCC, enabling the use of nearly the whole detector area for photon detection, which is of paramount importance for excellent image quality. At the opposite side of the substrate, four ASICs with 272 μm bump pitch are flip chip solder assembled to the LTCC substrate including underfilling, and a few SMD (Surface Mount Device) components are mounted. A scintillator crystal array on top of the SiPMs converts gamma rays (511 keV photons produced from positron-electron annihilation) into light. We assume that the LTCC substrates and all components are fully MRI compatible, which is important for the integration of PET with MRI without mutual interference. The paper elucidates the impact of the used technology on the performance of advanced PET/MRI detector modules.

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