Evaluation of Low Stress Photo-Sensitive Spin On Dielectric Layers for Through Silicon Via (TSV) Copper Redistribution Layers

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000666-000698
Author(s):  
Christopher Jahnes ◽  
Eric Huenger ◽  
Scott Kisting
Keyword(s):  
Power Distribution ◽  
Flip Chip ◽  
Dielectric Materials ◽  
Back Side ◽  
Thermal Reliability ◽  
Dielectric Layers ◽  
Chip Size ◽  
Package Density ◽  
Silicon Vias ◽  
Wafer Thinning

To increase performance of semiconductor devices advances in packaging such as chip stacking (3D) and silicon carrier technologies (SoC) are being developed. Adaptation of these packaging fabrication methods offers the ability to incorporate functionality as well as provide memory and power distribution on one IC with increased signal bandwidth. An enabling element in both the stacking and silicon carrier technologies is through silicon vias (TSV) which electrically connect dies to a silicon carrier or via stacked chips (1). Creation of TSV involves via fabrication, wafer thinning and back side wafer finishing, to name a few, some of which are relatively new to semiconductor processing. Furthermore, because the wafer backside is accessible it can now be utilized to route wiring to further increase package density. The focus of this research was to evaluate photo-sensitive spin on dielectric materials (SOD) that can be used as the backside wiring levels, commonly referred to as redistribution layers (RDL) in TSV technologies. The two materials evaluated are; the epoxy based Dow INTERVIA™ 8023 Dielectric and the Benzocyclobutene (BCB) polymer, Dow CYCLOTENE™ 4000 product series. These dielectric materials have low stress and provide good planarization (2). Test vehicles with a chip size of 3.7 cm x 2.26 cm were fabricated with a 6 um wide copper RDL layer using the SOD materials of interest as well as conventional PECVD SiO2/SiN dielectric layers. The large chip size accommodated parallel Cu lines running 1.8 cm long with a spacing of 3 m and represented an aggressive shorting test for the SOD materials. It also enhances chip distortion after thinning and is evaluated for all three test vehicles. Chips were then electrically tested through simulated 260° C reflow cycles (for flip chip joining) and accelerated thermal reliability tests from −55° C to 125° C for 1000 cycles.

Multi-Stacked Flip Chips with Copper Plated Through Silicon Vias and Re-distribution for 3D System-in-Package Integration

2006 ◽  
Vol 970 ◽  
Author(s):  
Shi-Wei Ricky Lee ◽  
Ronald Hon
Keyword(s):  
Flip Chip ◽  
Three Dimensional ◽  
Back Side ◽  
Wafer Level ◽  
Flip Chips ◽  
Electrical Interconnection ◽  
Solder Balls ◽  
Original Size ◽  
Structure Lead ◽  
Silicon Vias

ABSTRACTThe study is a prototype design and fabrication of multi-stacked flip chip three dimensional packaging (3DP) with TSVs for interconnection. Three chips are stacked together to make a 3DP with solder bumped flip chips. TSVs are fabricated and distributed along the periphery of the middle chip. The TSVs are formed by dry etching, deep reactive ions etching (DRIE), with dimensions of 150 × 100 microns. The TSVs are plugged by copper plating. The filled TSVs are connected to the solder pads by extended pad patterns surrounding the top and the bottom of TSVs on both sides of the wafer for the middle chip. After pad patterning passivation and solder bumping, the wafer is sawed into chips for subsequent 3D stacked die assembly. Because the TSVs are located at the periphery of the middle chips and stretch across the saw street between adjacent chips, they will be sawed through their center to form two open TSVs (with half of the original size) for electrical interconnection between the front side and the back side of the middle chip. The top chip is made by the conventional solder bumped flip chip processes and the bottom chip is a carrier with some routing patterns. The three middle chips and top chip are stacked by a flip chip bonder and the solder balls are reflowed to form the 3DP structure. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented.

Monitoring of Wet Etch for Wafer Thinning and Via Reveal Process

2013 ◽  
Vol 2013 (1) ◽  
pp. 000008-000012
Author(s):  
Chuannan Bai ◽  
Eugene Shalyt ◽  
Guang Liang ◽  
Peter Bratin
Keyword(s):  
Process Control ◽  
Etch Rate ◽  
Back Side ◽  
Reaction Products ◽  
Product Characteristics ◽  
Pros And Cons ◽  
Last Stage ◽  
Silicon Vias ◽  
Wet Etch ◽  
Wafer Thinning

TSV (Through Silicon Vias) are usually formed and deposited as blind vias. As a last stage, vias are opened by thinning of the back side of the wafer. While the bulk of the silicon can be removed by both wet and dry methods, the final step of the “Via Reveal” process is predominantly performed by wet etch. Two commonly used types of etching solutions are anisotropic alkaline etch (KOH, TMAH, etc.) and isotropic etch (HF/HNO3, etc.). Etch rate, uniformity, and product characteristics strongly depend on the composition of solution: both original compounds and reaction products. This presentation describes different approaches for process control of both alkaline and acidic etch solutions using advanced spectroscopic models and potentiometry. Pros and cons of different approaches are discussed. Specific emphasis is placed on the monitoring of reaction products.

Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology

2010 ◽  
Author(s):  
K. Dickson ◽  
G. Lange ◽  
K. Erington ◽  
J. Ybarra
Keyword(s):  
Electron Beam ◽  
Flip Chip ◽  
Back Side ◽  
Soi Technology

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

Development of Organic Multi Chip Package for High Performance Application

2013 ◽  
Vol 2013 (1) ◽  
pp. 000414-000414 ◽  
Author(s):  
Noriyoshi Shimizu ◽  
Wataru Kaneda ◽  
Hiromu Arisaka ◽  
Naoyuki Koizumi ◽  
Satoshi Sunohara ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Metal Layer ◽  
Small Diameter ◽  
Organic Substrate ◽  
Back Side ◽  
Test Results ◽  
Manufacturing Method ◽  
Separate Step ◽  
High Performance Application

In recent years, it has become apparent that the conventional FC-BGA (Flip Chip Ball Grid Array) substrate manufacturing method (Electroless Cu plating, Desmear, Laser Drilling processing) is reaching its limits for finer wiring dimensions and narrower pitches of the flip chip pad. On the other hand, the demand for miniaturization and higher density continues to increase. Our solution is the Organic Multi Chip Package, a combined organic interposer and organic substrate. Unlike a conventional 2.5D interposer that is separately manufactured and then attached to a substrate PWB (Printed Wire Board), the interposer of our Organic Multi Chip Package is built directly onto an organic substrate. First normal build-up layers are laminated on both sides of the PWB core and metal traces formed by conventional semi-additive techniques. After the back side is coated with a typical SR layer for FC-BGA, the top surface and its laser-drilled vias are smoothed by CMP (Chemical Mechanical Polishing). A thin-film process is used to deposit the interposer's insulating resin layers. Then normal processes are applied to open small diameter vias and a metal seed layer is sputtered on. The wiring is patterned, and the metal traces are fully formed by plating. Finally, the Cu pads on the top layer are treated by OSP (Organic Solderability Preservative). In this paper we discuss results using a prototype 40 mm × 40 mm Organic Multi Chip Package. The prototype's organic substrate has a two-metal layer core with 100 μm diameter through-holes, two build-up layers on the chip side, and three plus a solder resist layer on the BGA side. The interposer has four wiring layers. Thus the structure of the prototype is 4+(2/2/3). For evaluation purposes, there are four patterns of lines and spaces on the interposer: 2 μm/2 μm, 3 μm/3 μm, 4 μm/4 μm, and 5 μm/5 μm. The metal trace thicknesses are 2.5 μm, via diameters are 10 μm, pad pitches are 40 μm, and the Cu pad diameters are 25 μm. These dimensions allow the Organic Multi Chip Package to easily make the pitch conversions of the IC to the PCB. With a 4+(2/2/3) structure, the Organic Multi Chip Package is asymmetric, raising concerns about package warping. However, the warping can be reduced by the optimization of structure and materials. In this way, we were able to connect a high pin-count logic chip to standard Wide I/O memory chips. We think that there are at least two obvious advantages of the Organic Multi Chip Package. The first is a total height reduction compared to a structure with a separate silicon interposer attached to a PWB substrate. The Organic Multi Chip Package, with its built-on interposer, eliminates the need for solder joints between the interposer and substrate. In addition, the fine resin layers make our interposer much thinner than a silicon interposer. The second advantage is simpler assembly. Our structure does not require the separate step of assembling an interposer to the substrate. Assembly costs should be lower and yields higher. In this paper we demonstrate the successful attainment of fine lines and spaces on the Organic Multi Chip Package. We also show and discuss reliability test results.

Underfill Dispensing for 3D Die Stacking with Through Silicon Vias

2012 ◽  
Vol 2012 (1) ◽  
pp. 000548-000553 ◽  
Author(s):  
Fuliang Le ◽  
S. W. Ricky Lee ◽  
Jingshen Wu ◽  
Matthew M. F. Yuen
Keyword(s):  
Flip Chip ◽  
Through Silicon Vias ◽  
Flip Chips ◽  
Solder Bumps ◽  
Die Stacking ◽  
Chip Carrier ◽  
On Chip ◽  
Silicon Vias ◽  
3D Package

In this paper, a 3D stacked-die package is developed for the miniaturization and integration of electronic devices. The developed package has a stacked flip-chip-on-chip structure and eight flip chips are arranged in four vertical layers using four silicon chip carriers with through silicon vias (TSVs). In each layer, two flip chips are mounted on the silicon chip carrier with 100 um solder bumps, and multiple TSVs are fabricated in each silicon chip carrier for underfill dispensing purpose. The 3D module with four stacked layers is sequentially assembled by the standard surface mount reflow process and finally mounted to a substrate. In the underfill process, conventional I-pass underfill is used to fill up the gaps of the bottom two layers as it has relatively fast spreading speed. For the top two chip carriers, underfill is dispensed through TSVs to fill the gaps. Unlike the conventional underfill process, the encapsulant in this case would not flow in the gaps by the capillary effect unless the dispensed materials can obtain enough kinetic energy to overcome the surface tension at the end of TSVs, and thus, smooth sidewall, proper dispensing settings and optimized TSV pattern are needed. After underfill, detailed inspections are performed to verify the quality of encapsulation. The results show that the combined I-pass/TSV underfill process gives void-free encapsulation and perfect fillets for the stacked 3D package.

Reliability Evaluation of CSP Using New Flip-Chip Bonding Technology: Both-Sided CSP and Single-Sided CSP

2002 ◽  
Author(s):  
Hideo Koguchi ◽  
Nipon Taweejun ◽  
Kazuto Nishida ◽  
Chie Sasaki
Keyword(s):  
Finite Element Method ◽  
Cross Section ◽  
Flip Chip ◽  
High Reliability ◽  
Reliability Evaluation ◽  
Thickness Direction ◽  
Material Parameters ◽  
Conductive Film ◽  
Chip Size ◽  
Bonding Technology

Chip-size packaging (CSP) attracts largely attentions due to its lighter, thinner and smaller size. In this study, the deformations and the stresses in the CSP fabricated by non-conductive film stud-bump direct interconnection (NSD) were analyzed. The reliability evaluation of single-sided CSP and both-sided CSP were investigated for heat cycles. The material parameters, i.e. stresses, strains and deformations, for achieving a high reliability of CSP were investigated using a finite element method and experiment. The dependency of the life in single-sided CSP and both-sided CSP on the thicknesses of IC and substrate could be expressed using a normal stress in the thickness direction and shear stress in the vertical cross section, respectively.

Formation of Through-Silicon-Vias by Laser Drilling and Deep Reactive Ion Etching

2004 ◽  
Author(s):  
Ronald Hon ◽  
Shawn X. D. Zhang ◽  
S. W. Ricky Lee
Keyword(s):  
Reactive Ion Etching ◽  
Three Dimensional ◽  
Laser Drilling ◽  
Wet Etching ◽  
Ion Etching ◽  
Through Silicon Vias ◽  
Deep Reactive Ion Etching ◽  
Definition Of ◽  
Silicon Vias ◽  
Wafer Thinning

The focus of this study is on the fabrication of through silicon vias (TSV) for three dimensional packaging. According to IPC-6016, the definition of microvias is a hole with a diameter of less than or equal to 150 μm. In order to meet this requirement, laser drilling and deep reactive ion etching (but not wet etching) are used to make the microvias. Comparisons between these two different methods are carried out in terms of wall straightness, smoothness, smallest via produced and time needed for fabrication. In addition, discussion on wafer thinning for making through silicon microvias is given as well.

FUNDAMENTALS OF THE SQUEEZE-FLOW BETWEEN A HEAT SINK AND A FLIP-CHIP

2008 ◽  
Vol 32 (3-4) ◽  
pp. 467-486 ◽  
Author(s):  
M.A. Marois ◽  
M. Lacroix
Keyword(s):  
Heat Sink ◽  
Flip Chip ◽  
String Model ◽  
Thermal Interface Material ◽  
Squeeze Flow ◽  
Back Side ◽  
Two Dimensional ◽  
Particle Volume ◽  
Volume Fractions ◽  
Drop Flow

The paper presents the fundamentals of the squeeze-flow of the thermal interface material (TIM) that takes place during the pressing of a heat sink to the back side of a flip-chip is studied. A two-dimensional string model is developed for predicting the time-varying plate separation and squeeze-rate in terms of the squeeze force. The predictions are compared to a one-dimensional string model and to a squeeze-drop flow model. Results indicate that the flow resulting from the squeezing of a string of TIM between two rigid plates is truly two-dimensional. The effect of surface tension and of the heat transfer is found to be negligible under the assembly conditions. The flow behaviour of the TIM with suspensions of high thermal conductivity particles is also investigated. It is shown that the fluid remains Newtonian for particle volume fractions smaller than 30%. For volume fractions larger than 30%, the fluid becomes Non-Newtonian during the early stages of the squeezing process, i.e. for t ≤ 1s. In the later stages however (t > 10s), the fluid may be considered Newtonian.

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