Enhanced 32-Bit Adder Implementation using Different Configurations of Adders

Adders play a essential role with in the digital signal process systems. The 32-bit configuration is commonly used in few computerized systems and processors. In this paper, detail study about the implementation of 32-bit adders like Ripple Carry Adder (RCA), Carry Select adder (CSLA) and Carry Increment adder (CINA) is done for various configurational full adders using VHDL. The outcomes are acquired by executing VHDL in Xilinx ISE 14.5 with speed grade -5 of Spartan 3E family device.

A Processing Method of Identifying Spectrum of Shock Load for the Combustion Gas Stream

The spectrum of the load component is retained and the spectrum of other components are eliminated by the identifying spectrum is processed with addition or subtraction in the frequency domain. The method avoids an error that Gibbs’ vibration is generated as the signals multiply each other in frequency domain is equivalent to the signals are convolution in time domain in the filtering. On the basis of Fourier transformation, the method only using addition or subtraction obtains useful frequency components. Compare with other processing methods, the processing result can satisfy the identifying requests. In practice, the method is simple and convenient and the operational error is less. It is a try for digital signal process.

SIP with TSV for Class 1 Medical Devices

The demand for greater performance of hearing instruments in smaller form factors continues to drive the need for miniaturization of microelectronic packages. This article reports how through-silicon-via (TSV) technology was used to shrink the size of a conventional digital signal process (DSP)-based system in package (SIP) used in the smallest in-the-ear hearing instruments. The conventional SIP is a heterogeneous multichip module containing a wire-bonded electrically erasable programmable read-only memory (EEPROM) die mounted atop a DSP flip-chip die along with 10 passive components built upon a high-density alumina substrate. The wire bonds of the conventional SIP, along with the extra space they require, are eliminated and replaced by TSV structures fabricated in the DSP integrated circuit (IC) wafer using the via-last method. A redistribution layer on the back side of the DSP IC enables direct attachment and electrical interconnection of the memory IC to the DSP IC. The result is a 23% smaller SIP with functionality demonstrated in hearing aid prototypes. This is believed to be the first demonstration of TSV in a heterogeneous hearing aid multichip module. This article describes the design approaches, materials, basic process steps, results, and challenges encountered in creating this novel TSV-SIP.

Application of DFG Model on SOPC Technology

HW/SW (hardware/software) co-design method based on analysis and optimization of DFG (data flow graphic) model is introduced for SOPC (System on a Programmable Chip) used for digital instrument design in this paper. The method is based on the DFG model of the digital signal process algorithm and implemented with SOPC technology. The DFG model could help designer to divide the function into hardware and software respectively, therefore, the optimizing analysis at system level and circuit level of a SOPC used for portable logic analyzer shows that the DFG model is very useful for not only optimizing architecture and power consumption, but also HW/SW co-design.