3D Wire Bondless Integration: The Future of Silicon Carbide (SiC) Packaging

2017 ◽  
Author(s):  
Sayan Seal ◽  
Andrea K. Wallace ◽  
John E. Zumbro ◽  
H. Alan Mantooth
Keyword(s):  
Electromagnetic Interference ◽  
Flip Chip ◽  
Wide Bandgap ◽  
Switching Losses ◽  
Wire Bonds ◽  
Electrical Interconnection ◽  
Power Modules ◽  
Chip Scale Package ◽  
Solder Balls ◽  
High Temperature Operation

Wide bandgap (WBG) semiconductors are revolutionizing the world of power electronics. They have the potential to bring about an unprecedented increase in power density. The ability to switch at ultrafast rates, coupled with the promise of high temperature operation, make these devices extremely desirable. However, having superior semiconductor devices will not automatically translate to superior package characteristics. In real applications, the performance of a power device is only as good as the package allows. One of the major drawbacks plaguing contemporary power modules is the wire-bonded interconnection. Wire bonds offer a high parasitic inductance. This paper presents a novel wire bondless SiC power MOSFET packaging technique. A commercially available bare die was reconfigured into a chip-scale package. The new form factor enabled the MOSFET to be bonded to a patterned FR4 substrate using flip-chip bonding. The electrical interconnection between the package and the substrate was established using solder balls — thus eliminating the requirement for wire bonds. The motivation for using a wire bondless method was a reduction in stray parasitic inductances and an increase in the thermo-mechanical reliability. Lower parasitic inductances will facilitate high switching frequencies which will promote miniaturization, a reduction in electromagnetic interference (EMI), and lead to lower switching losses. The proposed approach was demonstrated to reduce the parasitic loop inductance by a fctor of > 3× as compared with wire bonded modules.

Reliability Prediction of Area Array Solder Joints

2003 ◽  
Vol 125 (4) ◽  
pp. 562-568 ◽  
Author(s):  
Rainer Dudek ◽  
Ralf Do¨ring ◽  
Bernd Michel
Keyword(s):  
Geometric Modeling ◽  
Flip Chip ◽  
Failure Criteria ◽  
Temperature Fields ◽  
The Finite Element Method ◽  
Chip Technology ◽  
Array Technology ◽  
Chip Scale Package ◽  
Solder Balls

Packages for high pin counts using the ball grid array technology or its miniaturized version, the chip scale package, inherently require reliability concepts as an integral part of their development. This is especially true for the latter packages, if they are combined with the flip chip technology. Accordingly, thermal fatigue of the solder balls is frequently investigated by means of the finite element method. Various modeling assumptions and simplifications are common to restrict the calculation effort. Some of them, like geometric modeling assumptions, assumptions concerning the homogeneity of the cyclic temperature fields, simplified creep characterization of solder, and the related application of Manson-Coffin failure criteria, are discussed in the paper. The packages chosen for detailed analyses are a PBGA 272 and a FC-CSP 230.

Multi-Stacked Flip Chips with Copper Plated Through Silicon Vias and Re-distribution for 3D System-in-Package Integration

2006 ◽  
Vol 970 ◽  
Author(s):  
Shi-Wei Ricky Lee ◽  
Ronald Hon
Keyword(s):  
Flip Chip ◽  
Three Dimensional ◽  
Back Side ◽  
Wafer Level ◽  
Flip Chips ◽  
Electrical Interconnection ◽  
Solder Balls ◽  
Original Size ◽  
Structure Lead ◽  
Silicon Vias

ABSTRACTThe study is a prototype design and fabrication of multi-stacked flip chip three dimensional packaging (3DP) with TSVs for interconnection. Three chips are stacked together to make a 3DP with solder bumped flip chips. TSVs are fabricated and distributed along the periphery of the middle chip. The TSVs are formed by dry etching, deep reactive ions etching (DRIE), with dimensions of 150 × 100 microns. The TSVs are plugged by copper plating. The filled TSVs are connected to the solder pads by extended pad patterns surrounding the top and the bottom of TSVs on both sides of the wafer for the middle chip. After pad patterning passivation and solder bumping, the wafer is sawed into chips for subsequent 3D stacked die assembly. Because the TSVs are located at the periphery of the middle chips and stretch across the saw street between adjacent chips, they will be sawed through their center to form two open TSVs (with half of the original size) for electrical interconnection between the front side and the back side of the middle chip. The top chip is made by the conventional solder bumped flip chip processes and the bottom chip is a carrier with some routing patterns. The three middle chips and top chip are stacked by a flip chip bonder and the solder balls are reflowed to form the 3DP structure. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented.

Flip-chip Bonded SiC Power Devices on a Low Temperature Co-fired Ceramic (LTCC) Substrate for Next Generation Power Modules

2016 ◽  
Vol 2016 (HiTEC) ◽  
pp. 000159-000168 ◽  
Author(s):  
Sayan Seal ◽  
Michael D. Glover ◽  
H. Alan Mantooth
Keyword(s):  
Flip Chip ◽  
State Of The Art ◽  
Power Devices ◽  
Power Module ◽  
Wire Bonds ◽  
Power Modules ◽  
And Performance ◽  
Switching Characteristics ◽  
Generation Power ◽  
Ltcc Substrate

Abstract This paper explores the design and performance benefits of an LTCC-based power module using SiC power devices. The goal of the design is to achieve high power density with an improved level of reliability as compared to the state-of-the-art, especially at elevated operating temperatures. This will enable a more complete leveraging of the benefits of SiC semiconductor technology. The reliability of existing power modules under high thermo-mechanical stress is adversely affected by the presence of wire bonds and by delamination at the die attachment interface between the die and substrate. As power devices are driven at higher frequencies, wire bonds will inhibit performance by introducing ringing and large overshoots due to the parasitic inductances they introduce in the critical switching loops in the circuit. A flip-chip bonding process for bonding the power devices has been investigated in this paper as an alternative to wire-bonding. It was found that flip-chip interconnects not only improved the switching characteristics of the device, but also reduced thermo-mechanical stresses on the bonding interface.

SIP with TSV for Class 1 Medical Devices

2014 ◽  
Vol 2014 (1) ◽  
pp. 000313-000318
Author(s):  
Doug Link
Keyword(s):  
Flip Chip ◽  
Hearing Aid ◽  
Form Factors ◽  
Multichip Module ◽  
Back Side ◽  
Passive Components ◽  
Wire Bonds ◽  
Electrical Interconnection ◽  
Hearing Instruments ◽  
Class 1

The demand for greater performance of hearing instruments in smaller form factors continues to drive the need for miniaturization of microelectronic packages. Reported here is how TSV technology was used to shrink the size of a conventional DSP-based system in package (SIP) used in the smallest In-The-Ear (ITE) hearing instruments. The conventional SIP is a heterogeneous multichip module containing a wire bonded EEPROM die mounted atop a DSP flip chip die along with 10 passive components built upon a high density alumina substrate. The wire bonds of the conventional SIP, along with the extra space they require, are eliminated and replaced by TSV structures fabricated in the DSP IC wafer using the via last method. A redistribution layer on the back side of the DSP IC enables direct attachment and electrical interconnection of the memory IC to the DSP IC. The result is a 23% smaller SIP with functionality demonstrated in hearing aid prototypes. This is believed to be the first demonstration of TSV in a heterogeneous hearing aid multichip module. This paper describes the design approach, materials, basic process steps, results, and challenges encountered in creating this novel TSV-SIP.

Global Technology Survey of Anisotropic Conductive Interconnect Technologies, Past Present and Future - An Industry Intellectual Property Approach

2010 ◽  
Vol 2010 (1) ◽  
pp. 000098-000104
Author(s):  
Edmar M. Amaya ◽  
Gene A. Lang
Keyword(s):  
Intellectual Property ◽  
Flip Chip ◽  
Low Cost ◽  
Assembly Lines ◽  
Wire Bonds ◽  
3D Packaging ◽  
Solder Balls ◽  
Cost Efficient ◽  
Commercial Applications ◽  
On Chip

Anisotropic Conductive Technologies (ACT), and materials comprising films and epoxies, started as a solution to provide low-cost reliable interconnection for glass displays on small, cheap calculators. ACT is mature now and have encroached into other types of technologies, especially Flip Chip, LEDs, OELDS, MEMS, 3D packaging, Microwave/RF and Optics. In today's assembly lines, ACT have replaced gold bumps, solder balls, wire bonds, and created new, more cost efficient chip-on chip, chip-on-film, chip-on-board, and chip-on-ceramic applications. Companies around the globe have realized the advantages of this technology to control thermal management, failures, speed of production, and they have vigorously engaged in protection of their intellectual property. The author will present a survey of the technology from a patent, trade secret, and licensing approach. In his analyses of the findings, he will show how different companies around the globe are using ACT to solve their interconnection needs. The author will also present future types of ACT and its uses for military, aerospace, and other commercial applications.

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages (WLCSP)

2011 ◽  
Author(s):  
Pushkraj Tumne ◽  
Vikram Venkatadri ◽  
Santosh Kudtarkar ◽  
Michael Delaus ◽  
Daryl Santos ◽  
...  
Keyword(s):  
Flip Chip ◽  
Bulk Solder ◽  
Consumer Electronics ◽  
Drop Test ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Wafer Level ◽  
Cross Sectional ◽  
Right Censored Data ◽  
Solder Balls

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

2002 ◽  
Vol 124 (3) ◽  
pp. 205-211 ◽  
Author(s):  
John H. Lau ◽  
S. W. Ricky Lee ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Test Results ◽  
Pcb Assembly ◽  
Creep Analysis ◽  
Chip Scale Package ◽  
Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

scholarly journals Growth Kinetics of Reaction Layers in Flip Chip Joints with Cu-cored Lead-free Solder Balls

2004 ◽  
Vol 45 (3) ◽  
pp. 754-758 ◽  
Author(s):  
Ikuo Shohji ◽  
Yuji Shiratori ◽  
Hiroshi Yoshida ◽  
Masahiko Mizukami ◽  
Akira Ichida
Keyword(s):  
Growth Kinetics ◽  
Flip Chip ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Balls ◽  
Free Solder ◽  
Kinetics Of Reaction ◽  
Kinetics Of
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