Lithography Process Challenges for 3D and 2.5D Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000398-000424
Author(s):  
Doug Shelton ◽  
Tomii Kume
Keyword(s):  
High Resolution ◽  
Process Optimization ◽  
Mass Production ◽  
Low Cost ◽  
High Density ◽  
Through Silicon Via ◽  
Key Technology ◽  
Lithography Process ◽  
Advanced Packaging

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon will continue its discussion of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications.

Lithography Process Optimization for 3D and 2.5D Applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000790-000793 ◽  
Author(s):  
Doug Shelton ◽  
Tomii Kume
Keyword(s):  
High Resolution ◽  
Process Optimization ◽  
Preliminary Data ◽  
Mass Production ◽  
Low Cost ◽  
High Density ◽  
Through Silicon Via ◽  
Key Technology ◽  
Lithography Process ◽  
Advanced Packaging

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon continues its investigation of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications also preliminary data illustrating 450 mm wafer process challenges.

Advanced Manufacturing Technology for Fan-Out Wafer Level Packaging

2015 ◽  
Vol 2015 (1) ◽  
pp. 000251-000255 ◽  
Author(s):  
Doug Shelton
Keyword(s):  
High Resolution ◽  
Mass Production ◽  
High Density ◽  
Advanced Manufacturing Technology ◽  
Successful Implementation ◽  
Advanced Manufacturing ◽  
Wafer Level ◽  
Process Technology ◽  
Key Technology ◽  
Wafer Level Packaging

Advanced process technology is required to develop and enable mass production of Fan-Out Wafer-Level Packaging (FOWLP) solutions for high-density 3D and 2.5D packaging. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies and has developed key technology for Canon Litho Systems to support the most challenging processes. In this paper, Canon will present process optimization results for high-resolution patterning of wafers across large topography as well as solutions that enable litho systems to compensate for FOWLP grid error due to die placement errors.

Advanced Process Technology for 3D and 2.5D Applications

2014 ◽  
Vol 2014 (1) ◽  
pp. 000905-000911
Author(s):  
Doug Shelton ◽  
Tomii Kume ◽  
Charles Wang ◽  
Alex Hubbard ◽  
Cody Murray ◽  
...  
Keyword(s):  
Process Optimization ◽  
Mass Production ◽  
High Density ◽  
Process Technology ◽  
Profile Control ◽  
Additional Product

Advanced process technology is required to develop and enable mass production of high-density 3D and 2.5D interconnect technologies. In this paper, Canon and IBM @ Albany NanoTech will present process optimization results for lithography applications requiring precise thick-resist profile control and precise overlay accuracy of distorted patterns on bonded process wafers. Canon will also provide additional product updates from Canon Anelva.

Contact hole shrink and multiplication by directed self-assembly of block copolymers: from material to integration

2015 ◽  
Vol 1750 ◽  
Author(s):  
Raluca Tiron ◽  
Xavier Chevalier ◽  
Ahmed Gharbi ◽  
Maxime Argoud ◽  
Patricia Pimenta-Barros ◽  
...  
Keyword(s):  
High Resolution ◽  
Block Copolymers ◽  
Self Assembly ◽  
Low Cost ◽  
Advanced Characterization ◽  
High Potential ◽  
Assembly Process ◽  
Promising Alternative ◽  
Lithography Process ◽  
Pattern Density

ABSTRACTDensity multiplication of patterned templates by directed self-assembly (DSA) of block copolymers (BCP) stands out as a promising alternative to overcome the limitation of conventional lithography. Using the 300mm pilot line available in LETI and Arkema’s materials, the main objective is to integrate DSA directly into the conventional CMOS lithography process in order to achieve high resolution and pattern density multiplication at a low cost. Thus we investigate the potential of DSA to address contact and via level patterning by performing either CD shrink or contact multiplication. Our approach is based on the graphoepitaxy of PS-b-PMMA block copolymers. Lithographic performances of block copolymers are evaluated both for contact shrink and contact doubling. Furthermore, advanced characterization technics are used to monitor in-film self-assembly process. These results show that DSA has a high potential to be integrated directly into the conventional CMOS lithography process in order to achieve high resolution contact holes.

Realization of Mass Production of Microlens Array by Hot Embossing on Silicon Substrate

2010 ◽  
Vol 139-141 ◽  
pp. 1562-1565
Author(s):  
Xi Qiu Fan
Keyword(s):  
High Resolution ◽  
High Throughput ◽  
Silicon Substrate ◽  
Mass Production ◽  
Low Cost ◽  
Microlens Array ◽  
Hot Embossing ◽  
High Fidelity ◽  
Optical Performance ◽  
Large Area

Tradition lithographic techniques to produce micrlens array are complicated and time consuming. Due to the capability to replicate nanostructures repeatedly in a large area with high resolution and uniformity, hot embossing has been recognized as one of the promising approaches to fabricate microlens array with high throughput and low cost. This paper introduces processes to realize fabricating microlens array in mass production by direct hot embossing on silicon substrate. The mold is fabricated by multi-photolithography and etching steps and polymethyl methacrylate (PMMA) is chosen as the resist. Processes include coating, heating, pressing, etc. Fidelity and optical performance of the embossed microlens array were measured. High fidelity and fine optical performance of the embossed microlens array demonstrate the possibility of hot embossing to fabricate microlens array in mass production.

Embossing on Epoxy Thermoset Polymer Using SiO2 Coated Nickel Template

2007 ◽  
Vol 539-543 ◽  
pp. 968-973 ◽  
Author(s):  
Kyeong Jae Byeon ◽  
Sung Hoon Hong ◽  
Ki Yeon Yang ◽  
Deok Kee Kim ◽  
Heon Lee
Keyword(s):  
Mass Production ◽  
Seed Layer ◽  
Low Cost ◽  
Pmma Layer ◽  
Key Technology ◽  
Quartz Template ◽  
Mechanical Durability ◽  
Thermoset Polymer ◽  
Surface Protrusion ◽  
Si Wafer

Embossing or imprint lithography is the key-technology for the mass production of nanosized structures with low cost. Currently Si or quartz template which is produced by e-beam or DUV lithography and reactive ion etching, is used. However they are very expensive and easily damaged due to their brittleness. On the other hand, Ni template has high mechanical durability and can be fabricated with low cost by electroplating. However, one of the key obstacles of Ni template is poor antistiction property, when it is used with sticky thermoset polymer. Due to its poor antistiction property, detachment of Ni template from epoxy substrate is one of the key obstacles. In this experiment, quartz template with 150nm to 1μm sized surface protrusion was fabricated and used to emboss the PMMA coated Si wafer. Then the imprinted PMMA layer was coated with metal seed layer and electroplating of Ni was followed to fabricate Ni template with 150nm to 1μm sized patterns. In order to form antistiction layer on Ni template, SAM antistiction layer was formed on SiO2 coated Ni template. As a result, nano patterns could be successfully transferred to sticky thermoset polymer using Ni template without any degradation of antistiction property.

Embossing on Epoxy Thermoset Polymer Using SiO2 Coated Nickel Template

2007 ◽  
Vol 539-543 ◽  
pp. 3580-3585
Author(s):  
Kyeong Jae Byeon ◽  
Sung Hoon Hong ◽  
Ki Yeon Yang ◽  
Deok Kee Kim ◽  
Heon Lee
Keyword(s):  
Mass Production ◽  
Seed Layer ◽  
Low Cost ◽  
Pmma Layer ◽  
Key Technology ◽  
Quartz Template ◽  
Mechanical Durability ◽  
Thermoset Polymer ◽  
Surface Protrusion ◽  
Si Wafer

Embossing or imprint lithography is the key-technology for the mass production of nanosized structures with low cost. Currently Si or quartz template which is produced by e-beam or DUV lithography and reactive ion etching, is used. However they are very expensive and easily damaged due to their brittleness. On the other hand, Ni template has high mechanical durability and can be fabricated with low cost by electroplating. However, one of the key obstacles of Ni template is poor antistiction property, when it is used with sticky thermoset polymer. Due to its poor antistiction property, detachment of Ni template from epoxy substrate is one of the key obstacles. In this experiment, quartz template with 150nm to 1μm sized surface protrusion was fabricated and used to emboss the PMMA coated Si wafer. Then the imprinted PMMA layer was coated with metal seed layer and electroplating of Ni was followed to fabricate Ni template with 150nm to 1μm sized patterns. In order to form antistiction layer on Ni template, SAM antistiction layer was formed on SiO2 coated Ni template. As a result, nano patterns could be successfully transferred to sticky thermoset polymer using Ni template without any degradation of antistiction property.

Enhancements to Picosecond Acoustic Metrology for application in FO-WLP Process

2018 ◽  
Vol 2018 (1) ◽  
pp. 000212-000216
Author(s):  
M. Mehendale ◽  
R. Mair ◽  
J. Chen ◽  
J. Tan ◽  
J. Dai ◽  
...  
Keyword(s):  
High Resolution ◽  
Cross Section ◽  
Large Scale ◽  
Low Cost ◽  
Critical Role ◽  
Under Bump Metallization ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Advanced Packaging ◽  
Line Space

Abstract Fan out wafer level packaging (FO-WLP) is one of the fastest growing advanced packaging segments due to its versatility for a wide variety of applications. It's compatibility with large scale, low cost, ultra-thin and high-density packages has made it very attractive. Cu redistribution layer and multiple metal under bump metallization stack play critical role in the FO-WLP process especially with shrinking line/space size and increasing density. We previously discussed the adaptation of PULSE™ technology, with the integration of a visible reflectometer and high resolution camera as a comprehensive in-line metrology tool for the advanced packaging applications. In this paper, we present results from some recent work on enhancements to the configuration for measurements of very thick, rough RDL films. The modifications provided significant improvement (9×) to throughput while maintaining gage capable repeatability. Cross-section SEM measurements on 1μm RDL structures were used to validate the extendibility of the technique.

Ultra High 3D Capacitors Values with High Volume Efficiency and Outstanding Stability

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001163-001191
Author(s):  
Catherine Bunel ◽  
Franck Murray
Keyword(s):  
Mass Production ◽  
High Reliability ◽  
High Volume ◽  
Volumetric Efficiency ◽  
Key Technology ◽  
Passive Devices ◽  
Package Size ◽  
Advanced Packaging ◽  
High Level ◽  
Volume Efficiency

IPDIA's primary effort is to develop innovative 3D technologies to integrate Passive Devices .One of their key technology drivers is the trench high-density capacitor. After introducing the 250nF/mm2 in mass production, it's now the turn to launch outstanding performances with a new worldwide record of 550nF/mm2. With the advanced packaging solutions using very thin dies stacking ,combining a high level of capacitance integration and high volumetric efficiency, this achievement will enable to extend the range of high reliability Silicon Capacitor values up to 10 μF in a package size 3.4mm*2.4mm*1.4mm and even smaller . This paper will provide the details to prove that the former ambitious target of 2 μF/mm3 is now close to reality.

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