Replacing the PECVD-SiO2 in the through-silicon via of high-density 3D LSIs with highly scalable low cost organic liner: Merits and demerits

2014 ◽  
Author(s):  
Murugesan Mariappan ◽  
Takafumi Fukushima ◽  
JiChel Beatrix ◽  
Hiroyuki Hashimoto ◽  
Yutaka Sato ◽  
...  
Keyword(s):  
Low Cost ◽  
High Density ◽  
Through Silicon Via

Lithography Process Challenges for 3D and 2.5D Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000398-000424
Author(s):  
Doug Shelton ◽  
Tomii Kume
Keyword(s):  
High Resolution ◽  
Process Optimization ◽  
Mass Production ◽  
Low Cost ◽  
High Density ◽  
Through Silicon Via ◽  
Key Technology ◽  
Lithography Process ◽  
Advanced Packaging

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon will continue its discussion of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications.

Lithography Process Optimization for 3D and 2.5D Applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000790-000793 ◽  
Author(s):  
Doug Shelton ◽  
Tomii Kume
Keyword(s):  
High Resolution ◽  
Process Optimization ◽  
Preliminary Data ◽  
Mass Production ◽  
Low Cost ◽  
High Density ◽  
Through Silicon Via ◽  
Key Technology ◽  
Lithography Process ◽  
Advanced Packaging

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon continues its investigation of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications also preliminary data illustrating 450 mm wafer process challenges.

Understanding and Optimizing Hybrid SSD with High-Density and Low-Cost Flash Memory

2021 ◽  
Author(s):  
Liang Shi ◽  
Longfei Luo ◽  
Yina Lv ◽  
Shicheng Li ◽  
Changlong Li ◽  
...  
Keyword(s):  
Flash Memory ◽  
Low Cost ◽  
High Density

scholarly journals ELECTROTHERMAL EFFECTS IN HIGH DENSITY THROUGH SILICON VIA (TSV) ARRAYS

2011 ◽  
Vol 115 ◽  
pp. 223-242 ◽  
Author(s):  
Wen-Sheng Zhao ◽  
Xiao-Peng Wang ◽  
Wen-Yan Yin
Keyword(s):  
High Density ◽  
Through Silicon Via ◽  
Electrothermal Effects

Flipchip Bonding of Si Chip on Flexible PEN Foil using Novel Electronic 100 μm Pitch Fan-out Circuitry

2007 ◽  
Vol 1030 ◽  
Author(s):  
Jeroen van den Brand ◽  
Erik Veninga ◽  
Roel Kusters ◽  
Tomas Podprocky ◽  
Andreas Dietzel
Keyword(s):  
Thick Film ◽  
Low Cost ◽  
Cost Effective ◽  
High Density ◽  
Polyethylene Naphthalate ◽  
Electronic Circuitry ◽  
Effective Technology

AbstractA novel, cost effective technology to manufacture high density embedded electronic circuitry is demonstrated. The process consists of laser photoablation of the circuitry into a substrate through a mask and subsequent filling using a polymer thick film paste. Because the volume of the substrate is used it is possible to make thick and thereby highly conductive lines using low cost materials and processes. The process is demonstrated for a fan out circuitry in 100 µm thick polyethylene naphthalate (PEN). The fan out circuitry has linewidths of 50 µm and line spacings of 100 µm. The usability of the circuitry is demonstrated by the successful flipchip bonding of a thinned Si daisy chain dummy chip with 176 IO's.

Low Cost Recursive Localization scheme for High Density Wireless Sensor Networks

2020 ◽  
pp. 263-285
Author(s):  
Badia Bouhdid ◽  
Wafa Akkari ◽  
Sofien Gannouni
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Density ◽  
Communication Overhead ◽  
Localization Algorithm ◽  
Localization Accuracy ◽  
Localization Scheme ◽  
Implementation Costs ◽  
Cost Effective Alternative ◽  
Algorithm Implementation

While existing localization approaches mainly focus on enhancing the accuracy, particular attention has recently been given to reducing the localization algorithm implementation costs. To obtain a tradeoff between location accuracy and implementation cost, recursive localization approaches are being pursued as a cost-effective alternative to the more expensive localization approaches. In the recursive approach, localization information increases progressively as new nodes compute their positions and become themselves reference nodes. A strategy is then required to control and maintain the distribution of these new reference nodes. The lack of such a strategy leads, especially in high density networks, to wasted energy, important communication overhead and even impacts the localization accuracy. In this paper, the authors propose an efficient recursive localization approach that reduces the energy consumption, the execution time, and the communication overhead, yet it increases the localization accuracy through an adequate distribution of reference nodes within the network.

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

A TXV-less Packaging Platform for the Era of IoTs

2015 ◽  
Vol 2015 (1) ◽  
pp. 1-5 ◽  
Author(s):  
Dyi-Chung Hu ◽  
Yu-Min Lin ◽  
Hsiang Hung Chang ◽  
Tao-Chih Chang ◽  
Wei-Chung Lo ◽  
...  
Keyword(s):  
Low Cost ◽  
High Density ◽  
The Other ◽  
Electrical Performance ◽  
Test Vehicle ◽  
Technology Infrastructure ◽  
Fine Line ◽  
Large Panel ◽  
Line Technology ◽  
Test Chips

A new concept of packaging platform calls eHDF (embedded high density film), that without any TXVs is been proposed. The eHDF uses the technology from two categories; one utilize the semiconductor fine line technology infrastructure and the other takes the advantage of laminate organic large panel process infrastructure. Hence, the fine line, better electrical performance and low cost requirements can be addressed at the same time by the eHDF packaging platform. In this paper, a test vehicle based on eHDF structure will be built and modules assembly with test chips on eHDF substrate will be performed.

Sepiolite as a nanofiller to improve mechanical and thermal behavior of recycled high-density polyethylene

2020 ◽  
Vol 36 (3) ◽  
pp. 185-195 ◽  
Author(s):  
Negin Farshchi ◽  
Yalda K Ostad
Keyword(s):  
Thermal Behavior ◽  
High Density Polyethylene ◽  
Low Cost ◽  
Process Condition ◽  
Softening Temperature ◽  
High Density ◽  
Plastic Pollution ◽  
Scanning Calorimetry ◽  
Melt Flow Rate ◽  
Recycled Hdpe

Regarding the current demand for controlling plastic pollution, recycling of polymer sounds a promising solution. However, recycling causes mechanical and thermal shortcomings in polymers. Addition of nanoparticles to recycled materials may overcome these shortcomings. Nanocomposites can be achieved either by blending or through polymerization. Sepiolite as a nanoparticle enhances the thermal properties of polymers. In this study, the effect of sepiolite as a nanoparticle has been investigated on the thermal and mechanical behavior of recycled high-density polyethylene (HDPE). Hardness, density, Vicat softening temperature, melt flow rate (MFR), and differential scanning calorimetry has been investigated on recycled HDPE containing different amount of sepiolite. Results showed that both the amount of recycled HDPE and the sepiolite content affect the mechanical and thermal behavior of samples. Increasing the amount of recycled component resulted in increasing of MFR, a slight increase in density, and decrease in Vicat softening point, hardness, melting temperature, and degree of crystallization. As an opposite effect of these to factors on crystallinity of HDPE, sepiolite content has better effects to be considered separately for each recycle content. Sepiolite can be introduced as a low-cost reinforcement filler in recycling industry for tuning new compositions based on process condition, or vice versa.

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