Advanced Process Technology for 3D and 2.5D Applications

2014 ◽  
Vol 2014 (1) ◽  
pp. 000905-000911
Author(s):  
Doug Shelton ◽  
Tomii Kume ◽  
Charles Wang ◽  
Alex Hubbard ◽  
Cody Murray ◽  
...  
Keyword(s):  
Process Optimization ◽  
Mass Production ◽  
High Density ◽  
Process Technology ◽  
Profile Control ◽  
Additional Product

Advanced process technology is required to develop and enable mass production of high-density 3D and 2.5D interconnect technologies. In this paper, Canon and IBM @ Albany NanoTech will present process optimization results for lithography applications requiring precise thick-resist profile control and precise overlay accuracy of distorted patterns on bonded process wafers. Canon will also provide additional product updates from Canon Anelva.

Lithography Process Challenges for 3D and 2.5D Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000398-000424
Author(s):  
Doug Shelton ◽  
Tomii Kume
Keyword(s):  
High Resolution ◽  
Process Optimization ◽  
Mass Production ◽  
Low Cost ◽  
High Density ◽  
Through Silicon Via ◽  
Key Technology ◽  
Lithography Process ◽  
Advanced Packaging

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon will continue its discussion of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications.

Lithography Process Optimization for 3D and 2.5D Applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000790-000793 ◽  
Author(s):  
Doug Shelton ◽  
Tomii Kume
Keyword(s):  
High Resolution ◽  
Process Optimization ◽  
Preliminary Data ◽  
Mass Production ◽  
Low Cost ◽  
High Density ◽  
Through Silicon Via ◽  
Key Technology ◽  
Lithography Process ◽  
Advanced Packaging

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon continues its investigation of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications also preliminary data illustrating 450 mm wafer process challenges.

Advanced Manufacturing Technology for Fan-Out Wafer Level Packaging

2015 ◽  
Vol 2015 (1) ◽  
pp. 000251-000255 ◽  
Author(s):  
Doug Shelton
Keyword(s):  
High Resolution ◽  
Mass Production ◽  
High Density ◽  
Advanced Manufacturing Technology ◽  
Successful Implementation ◽  
Advanced Manufacturing ◽  
Wafer Level ◽  
Process Technology ◽  
Key Technology ◽  
Wafer Level Packaging

Advanced process technology is required to develop and enable mass production of Fan-Out Wafer-Level Packaging (FOWLP) solutions for high-density 3D and 2.5D packaging. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies and has developed key technology for Canon Litho Systems to support the most challenging processes. In this paper, Canon will present process optimization results for high-resolution patterning of wafers across large topography as well as solutions that enable litho systems to compensate for FOWLP grid error due to die placement errors.

Manufacturability Study for Etching High-Density BST/Pt Capacitors

2000 ◽  
Vol 655 ◽  
Author(s):  
Jay Hwang
Keyword(s):  
High Temperature ◽  
Etch Rate ◽  
Control Process ◽  
High Density ◽  
Wafer Surface ◽  
Plasma Chamber ◽  
Reactive Plasma ◽  
Pt Electrodes ◽  
Profile Control

AbstractProfile control, process repeatability and productivity concerns in etching Pt electrodes are reviewed specifically for application in fabricating high-density BST/Pt capacitors. The approach of using a high temperature cathode in a high-density reactive plasma chamber has produced a repeatable >85° Pt profile, stable etch rate and low particle results over a 500-wafer marathon test. A “corrosion-like” BST defect can be prevented by adding a post etch treatment to remove any corrosive residue from the wafer surface. A feasible manufacturing solution for etching BST/Pt capacitors for future high-density DRAM application is demonstrated.

High Digital Speed Level-2 Interconnections via a New Microcontact Design

2001 ◽  
Author(s):  
Dariusz R. Pryputniewicz ◽  
Dimitry G. Grabbe ◽  
Ryszard J. Pryputniewicz
Keyword(s):  
Process Optimization ◽  
Electronic Packaging ◽  
High Density ◽  
Density Level ◽  
Speed Level ◽  
Material Utilization ◽  
Level 2

Abstract Requirements for high digital speed, high density, level-2 interconnections have led to development of a new microcontact. Design of this microcontact allows for separable and reusable interconnections. In this paper, we discuss methodology used to develop the microcontact, allowing 100% material utilization, present its design, including analysis and process optimization, and summarize its characteristics as they relate to electronic packaging.

Growth of SiC Microwires through Si Microwires Carburization

2011 ◽  
Vol 679-680 ◽  
pp. 512-515 ◽  
Author(s):  
Maelig Ollivier ◽  
Arnaud Mantoux ◽  
Edwige Bano ◽  
Konstantinos Rogdakis ◽  
Konstantinos Zekentes ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Raman Spectroscopy ◽  
Process Optimization ◽  
Gold Catalyst ◽  
Stacking Faults ◽  
Morphological Characterization ◽  
High Density ◽  
Silicon Microwires

Silicon microwires (MWs) previously synthesized using the VLS method with gold catalyst are being carburized at 1100°C under methane aiming to their conversion to SiC. SEM, TEM as well as XPS and Raman spectroscopy were used for structural and morphological characterization. After carburization achievement, SiC is found to be polycrystalline with a high density of stacking faults associated to an increase of surface roughness. Directions for the carburization process optimization are given.

scholarly journals Electrical Screening Method of VNAND Flash Channel Hole Bending Defects

2021 ◽  
Author(s):  
Dooyeun Jung ◽  
Youngha Choi ◽  
Jae In Lee ◽  
Bu-il Nam ◽  
Ki-Young Dong ◽  
...  
Keyword(s):  
Leakage Current ◽  
Flash Memory ◽  
Mass Production ◽  
Storage Systems ◽  
Screening Method ◽  
High Density ◽  
Horizontal Direction ◽  
Memory Cells ◽  
Adjacent Channel

Abstract A novel electrical screening method of channel hole bending (ChB) defects is proposed for the implementation of high-density vertical NAND (VNAND) flash memory. The ChB defects induces the leakage current between the two adjacent channel holes, which leads to fatal failure in storage systems. Thus, it is one of the key requirements for VNAND mass production to screen ChB defects electrically in advance. In the proposed screening method, a 3D checkerboard (CKBD) pattern is introduced, which consists of alternating programed (‘0’) and inhibited (‘1’) memory cells in a diagonal and horizontal direction. By measuring the leakage current between the channel holes, ChB defects can be successfully detected electrically.

Process Optimization of p+LDD in 130nm Process Technology using TCAD Simulation

2006 ◽  
Author(s):  
Hani Noorashiqin Abd Majid ◽  
Muhamad Rasat Muhamad ◽  
Albert Victor Kordesch ◽  
Chew Soon Aik
Keyword(s):  
Process Optimization ◽  
Process Technology ◽  
Tcad Simulation
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