A Seeded Channel Approach to Silicon-On-Insulator Technology

1985 ◽  
Vol 53 ◽  
Author(s):  
C. H. Ting ◽  
W. Baerg ◽  
H. Y. Lin ◽  
B. Siu ◽  
T. Hwa ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Channel Length ◽  
Crystalline Material ◽  
Silicon On Insulator ◽  
Thin Film Thickness ◽  
Laser Recrystallization ◽  
Computer Controlled ◽  
Channel Region ◽  
Standard Production ◽  
The Ideal

ABSTRACTA seeded channel approach was developed to avoid the short comings of the conventional SOI structure such as grain or sub-grain boundaries in the channel region, floating substrate effects, etc. In this approach, the gate of each FET is located above its own seed window to insure that single crystalline material is obtained for the channel region. The source and drain regions, however, are located in the recrystallized silicon over Si02 for improved isolation and minimizing junction capacitance. Recrystallization was obtained in 4" silicon wafers by using an Ar laser and a computer controlled X-Y stage with heated substrate holder. Problems encountered in laser recrystallization, such as, reflectivity variations over seed and SOI regions, surface ripples, pittings, etc., were eliminated by optimizing the thin film thickness of the isolation oxide, polysilicon, and the capping oxide. This technology was used successfully to fabricate FET devices using a standard production n-MOS process. Good device characteristics were obtainred using 400Å gate oxide and channel length ranging from 1um to 50um. The measured electron mobility in the channel region is, however still lower than the ideal bulk values.

Subboundary Free Submicronic Devices on Laser-Recrystallized Silicon Oninsulator

1984 ◽  
Vol 35 ◽  
Author(s):  
A.J. Auberton-Herve ◽  
J.P. Joly ◽  
J.M. Hode ◽  
J.C. Castagna
Keyword(s):  
Channel Length ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Mos Transistors ◽  
Seed Structure ◽  
Leakage Currents ◽  
Industrial Processing ◽  
Laser Recrystallization ◽  
Dynamic Performances ◽  
Lateral Epitaxy

ABSTRACTSeeding from bulk silicon (lateral epitaxy) has been used in Ar+ laser recrystallization to achieve subboundary free silicon on insulator areas. On these areas C.MOS devices have been performed using almost entirely the standard processing steps of a bulk micronic C-MOS technology. n -MOS transistors with channel length as small as 0.3 um have shown very small leakage currents. This is attributed especially to the lack of subboundaries. A 40 % increase in the dynamic performances in comparison with equivalent size C-MOS bulk devices has been obtained (93 ps of delay time per stage for a 101 stages ring oscillator with 0.8 μm of channel length). This is the best result presented so far on recrystallized SOI. No special requirements are needed in the lay out of the circuit with the chosen seed structure. Furthermore an industrial processing rate for the laser recrystallization processing has been achieved using an elliptical laser beam, a high scan velocity (30 cm/s) and a 100 μm line to line scan step (a 4' wafer in 4 minutes).

scholarly journals High-Drain Field Impacting Channel-Length Modulation Effect for Nano-Node N-Channel FinFETs

Crystals ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 262
Author(s):  
Mu-Chun Wang ◽  
Wen-Ching Hsieh ◽  
Chii-Ruey Lin ◽  
Wei-Lun Chu ◽  
Wen-Shiang Liao ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Gate Oxide ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Modulation Effect ◽  
Short Channel ◽  
Horizontal Drain ◽  
Source Voltage ◽  
Drain Field ◽  
28 Nm

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate voltage (VGS-VT) and the higher drain/source voltage VDS, the channel-length modulation (CLM) effect coming from the interaction impact of vertical gate field and horizontal drain field was increased and had to be revised well as the channel length L was decreased. Compared to the 28-nm MOSFETs, the interaction effect from the previous at the tested FinFETs on SOI substrate with the short-channel length L is lower than that at the 28-nm device, which means the interaction severity of both fields for nFinFETs is mitigated, but still necessary to be concerned.

The Effect of Channel-Protect Oxide on Laser Recrystallized Silicon-on-insulator MOS devices.

1986 ◽  
Vol 74 ◽  
Author(s):  
S. Sritharan ◽  
G. J. Collins ◽  
J. Fukumoto ◽  
N. Szluk ◽  
K. M. Jones ◽  
...  
Keyword(s):  
Oxide Layer ◽  
Silicon On Insulator ◽  
Bulk Silicon ◽  
Cmos Transistors ◽  
Mos Devices ◽  
Laser Recrystallization ◽  
Field Oxide ◽  
Channel Region ◽  
Seed Area

AbstractLatchup free lateral CMOS transistors with PMOS devices in the laser recrystallized silicon and the NMOS devices in the bulk silicon were fabricated. One micron thick field oxide isolates the PMOS devices in the recrystallized silicon from the NMOS devices in the bulk wafer. The seed area for recrystallization was used for the fabrication of the NMOS devices. An oxide layer of 0.1um thickness was used to protect the channel region of the NMOS devices during the laser recrystallization. The effect of this channel protect-oxide is discussed and the characteristics of the NMOS devices with and without the channel protect oxide are compared.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

2018 ◽  
Vol 32 (15) ◽  
pp. 1850157 ◽  
Author(s):  
Yue-Gie Liaw ◽  
Chii-Wen Chen ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Xuecheng Zou
Keyword(s):  
Gate Oxide ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Current Crowding ◽  
Crowding Effect ◽  
Short Channel ◽  
Channel Mobility ◽  
Channel Effect ◽  
193 Nm ◽  
Dry Etch

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.

Dynamics, Design, and Application of a Silicon-on-Insulator Technology Based Neuron

MRS Advances ◽  
2018 ◽  
Vol 3 (57-58) ◽  
pp. 3347-3357
Author(s):  
S. Dutta ◽  
T. Chavan ◽  
S. Shukla ◽  
V. Kumar ◽  
A. Shukla ◽  
...  
Keyword(s):  
Impact Ionization ◽  
Threshold Current ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Floating Body ◽  
Classification Problems ◽  
Floating Body Effect ◽  
Leakage Mechanism ◽  
Silicon Based ◽  
Length Scaling

Abstract:Spiking Neural Networks propose to mimic nature’s way of recognizing patterns and making decisions in a fuzzy manner. To develop such networks in hardware, a highly manufacturable technology is required. We have proposed a silicon-based leaky integrate and fire (LIF) neuron, on a sufficiently matured 32 nm CMOS silicon-on-insulator (SOI) technology. The floating body effect of the partially depleted (PD) SOI transistor is used to store “holes” generated by impact ionization in the floating body, which performs the “integrate” function. Recombination or equivalent hole loss mimics the “leak” functions. The “hole” storage reduces the source barrier to increase the transistor current. Upon reaching a threshold current level, an external circuit records a “firing” event and resets the SOI MOSFET by draining all the stored holes. In terms of application, the neuron is able to show classification problems with reasonable accuracy. We looked at the effect of scaling experimentally. Channel length scaling reduces voltage for impact ionization and enables sharper impact ionization producing significant designability of the neuron. A circuit equivalence is also demonstrated to understand the dynamics qualitatively. Three distinct regimes are observed during integration based on different hole leakage mechanism.

Sub-Continuum Simulations of Heat Conduction in Silicon-on-Insulator Transistors

1999 ◽  
Author(s):  
Per G. Sverdrup ◽  
Y. Sungtaek Ju ◽  
Kenneth E. Goodson
Keyword(s):  
Diffusion Equation ◽  
Free Path ◽  
Temperature Rise ◽  
Mean Free Path ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Heat Diffusion ◽  
Boltzmann Transport ◽  
Heat Diffusion Equation ◽  
Silicon Devices

Abstract The temperature rise in compact silicon devices is predicted at present by solving the heat diffusion equation based on Fourier’s law. The validity of this approach needs to be carefully examined for semiconductor devices in which the region of strongest electronphonon coupling is narrower than the phonon mean free path, Λ, and for devices in which Λ is comparable to or exceeds the dimensions of the device. Previous research estimated the effective phonon mean free path in silicon near room temperature to be near 300 nm, which is already comparable with the minimum feature size of current generation transistors. This work numerically integrates the phonon Boltzmann transport equation (BTE) within a two-dimensional Silicon-on-Insulator (SOI) transistor. The BTE is coupled with the classical heat diffusion equation, which is solved in the silicon dioxide layer beneath a transistor with a channel length of 400 nm. The sub-continuum simulations yield a peak temperature rise that is 159 percent larger than predictions using only the classical heat diffusion equation. This work will facilitate the development of simpler calculation strategies, which are appropriate for commercial device simulators.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

Modeling and Designing a Device Using MuGFETs

2008 ◽  
Author(s):  
V. K. Lamba ◽  
Derick Engles ◽  
S. S. Malik
Keyword(s):  
Gate Dielectric ◽  
Silicon Film ◽  
General Rule ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Radius Of Curvature ◽  
Short Channel ◽  
Dielectric Thickness ◽  
Fin Thickness

This work describes computer simulations of various, Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) with double and triple-gate structures, as well as gate-all-around devices. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. Here short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as Drain induced barrier lowering (DIBL), sub-threshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.

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