Subboundary Free Submicronic Devices on Laser-Recrystallized Silicon Oninsulator

1984 ◽  
Vol 35 ◽  
Author(s):  
A.J. Auberton-Herve ◽  
J.P. Joly ◽  
J.M. Hode ◽  
J.C. Castagna
Keyword(s):  
Channel Length ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Mos Transistors ◽  
Seed Structure ◽  
Leakage Currents ◽  
Industrial Processing ◽  
Laser Recrystallization ◽  
Dynamic Performances ◽  
Lateral Epitaxy

ABSTRACTSeeding from bulk silicon (lateral epitaxy) has been used in Ar+ laser recrystallization to achieve subboundary free silicon on insulator areas. On these areas C.MOS devices have been performed using almost entirely the standard processing steps of a bulk micronic C-MOS technology. n -MOS transistors with channel length as small as 0.3 um have shown very small leakage currents. This is attributed especially to the lack of subboundaries. A 40 % increase in the dynamic performances in comparison with equivalent size C-MOS bulk devices has been obtained (93 ps of delay time per stage for a 101 stages ring oscillator with 0.8 μm of channel length). This is the best result presented so far on recrystallized SOI. No special requirements are needed in the lay out of the circuit with the chosen seed structure. Furthermore an industrial processing rate for the laser recrystallization processing has been achieved using an elliptical laser beam, a high scan velocity (30 cm/s) and a 100 μm line to line scan step (a 4' wafer in 4 minutes).

A Seeded Channel Approach to Silicon-On-Insulator Technology

1985 ◽  
Vol 53 ◽  
Author(s):  
C. H. Ting ◽  
W. Baerg ◽  
H. Y. Lin ◽  
B. Siu ◽  
T. Hwa ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Channel Length ◽  
Crystalline Material ◽  
Silicon On Insulator ◽  
Thin Film Thickness ◽  
Laser Recrystallization ◽  
Computer Controlled ◽  
Channel Region ◽  
Standard Production ◽  
The Ideal

ABSTRACTA seeded channel approach was developed to avoid the short comings of the conventional SOI structure such as grain or sub-grain boundaries in the channel region, floating substrate effects, etc. In this approach, the gate of each FET is located above its own seed window to insure that single crystalline material is obtained for the channel region. The source and drain regions, however, are located in the recrystallized silicon over Si02 for improved isolation and minimizing junction capacitance. Recrystallization was obtained in 4" silicon wafers by using an Ar laser and a computer controlled X-Y stage with heated substrate holder. Problems encountered in laser recrystallization, such as, reflectivity variations over seed and SOI regions, surface ripples, pittings, etc., were eliminated by optimizing the thin film thickness of the isolation oxide, polysilicon, and the capping oxide. This technology was used successfully to fabricate FET devices using a standard production n-MOS process. Good device characteristics were obtainred using 400Å gate oxide and channel length ranging from 1um to 50um. The measured electron mobility in the channel region is, however still lower than the ideal bulk values.

3-Dimensional Integration Fabricated by Using Seeded Lateral Epitaxial Film on SiO2

1984 ◽  
Vol 33 ◽  
Author(s):  
N. Sasaki ◽  
T. Iwai ◽  
S. Kawamura ◽  
R. Mukai ◽  
K. Wada ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Silicon Film ◽  
Scanning Speed ◽  
Spot Size ◽  
Channel Length ◽  
Ring Oscillator ◽  
Seed Region ◽  
Power Supply Voltage ◽  
3 Dimensional ◽  
Laser Recrystallization

ABSTRACTSeeded lateral epitaxial laser-recrystallization of silicon film on SiO2 is applied to fabricate 3-dimensional (3-D) integrations: 3-D CMOS 7-stage ring oscillators. Top p-channel Si-gate SOI MOSFET's are fabricated in the seeded recrystallized silicon directly above bottom n-channel Si-gate bulk MOSFET's with insulator in between. The recrystallized silicon at the seed region can be utilized for buried contact to interconnect bottom and top MOSFET's. At the arsenic implantation step to fabricate source and drain of the bottom MOSFET's, ions are not implanted into the seed region to prevent heavy doping and crystal disorder there; otherwise the dopant diffuses laterally and residual crystal disorder disturbs the epitaxial recrystallization. After the laser-recrystallization, the seed region is implanted with phosphorus to interconnect the top and bottom MOSFET's.The Ar+ laser irradiation is performed with a 10 W power, a 50 μm spot size, a 13 cm/s scanning speed and a 13 μm step at 400 °C in air. Propagation delay of 460 psec is obtained for the seven stage 3-D CMOS ring oscillator at a power supply voltage of 17 V for a channel length of 3 μm and a channel width of 18 μm. In the seeded SOI films, grain boundary generation and crystal orientation can be controlled.

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

Dynamics, Design, and Application of a Silicon-on-Insulator Technology Based Neuron

MRS Advances ◽  
2018 ◽  
Vol 3 (57-58) ◽  
pp. 3347-3357
Author(s):  
S. Dutta ◽  
T. Chavan ◽  
S. Shukla ◽  
V. Kumar ◽  
A. Shukla ◽  
...  
Keyword(s):  
Impact Ionization ◽  
Threshold Current ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Floating Body ◽  
Classification Problems ◽  
Floating Body Effect ◽  
Leakage Mechanism ◽  
Silicon Based ◽  
Length Scaling

Abstract:Spiking Neural Networks propose to mimic nature’s way of recognizing patterns and making decisions in a fuzzy manner. To develop such networks in hardware, a highly manufacturable technology is required. We have proposed a silicon-based leaky integrate and fire (LIF) neuron, on a sufficiently matured 32 nm CMOS silicon-on-insulator (SOI) technology. The floating body effect of the partially depleted (PD) SOI transistor is used to store “holes” generated by impact ionization in the floating body, which performs the “integrate” function. Recombination or equivalent hole loss mimics the “leak” functions. The “hole” storage reduces the source barrier to increase the transistor current. Upon reaching a threshold current level, an external circuit records a “firing” event and resets the SOI MOSFET by draining all the stored holes. In terms of application, the neuron is able to show classification problems with reasonable accuracy. We looked at the effect of scaling experimentally. Channel length scaling reduces voltage for impact ionization and enables sharper impact ionization producing significant designability of the neuron. A circuit equivalence is also demonstrated to understand the dynamics qualitatively. Three distinct regimes are observed during integration based on different hole leakage mechanism.

Sub-Continuum Simulations of Heat Conduction in Silicon-on-Insulator Transistors

1999 ◽  
Author(s):  
Per G. Sverdrup ◽  
Y. Sungtaek Ju ◽  
Kenneth E. Goodson
Keyword(s):  
Diffusion Equation ◽  
Free Path ◽  
Temperature Rise ◽  
Mean Free Path ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Heat Diffusion ◽  
Boltzmann Transport ◽  
Heat Diffusion Equation ◽  
Silicon Devices

Abstract The temperature rise in compact silicon devices is predicted at present by solving the heat diffusion equation based on Fourier’s law. The validity of this approach needs to be carefully examined for semiconductor devices in which the region of strongest electronphonon coupling is narrower than the phonon mean free path, Λ, and for devices in which Λ is comparable to or exceeds the dimensions of the device. Previous research estimated the effective phonon mean free path in silicon near room temperature to be near 300 nm, which is already comparable with the minimum feature size of current generation transistors. This work numerically integrates the phonon Boltzmann transport equation (BTE) within a two-dimensional Silicon-on-Insulator (SOI) transistor. The BTE is coupled with the classical heat diffusion equation, which is solved in the silicon dioxide layer beneath a transistor with a channel length of 400 nm. The sub-continuum simulations yield a peak temperature rise that is 159 percent larger than predictions using only the classical heat diffusion equation. This work will facilitate the development of simpler calculation strategies, which are appropriate for commercial device simulators.

Modeling and Designing a Device Using MuGFETs

2008 ◽  
Author(s):  
V. K. Lamba ◽  
Derick Engles ◽  
S. S. Malik
Keyword(s):  
Gate Dielectric ◽  
Silicon Film ◽  
General Rule ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Radius Of Curvature ◽  
Short Channel ◽  
Dielectric Thickness ◽  
Fin Thickness

This work describes computer simulations of various, Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) with double and triple-gate structures, as well as gate-all-around devices. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. Here short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as Drain induced barrier lowering (DIBL), sub-threshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.

SiGe Heterostructures-on-Insulator Produced by Ge+-Ion Implantation and Subsequent Hydrogen Transfer

2007 ◽  
Vol 131-133 ◽  
pp. 143-148 ◽  
Author(s):  
Ida E. Tyschenko ◽  
A.G. Cherkov ◽  
M. Voelskow ◽  
V.P. Popov
Keyword(s):  
Hydrogen Transfer ◽  
Silicon Layer ◽  
Hole Mobility ◽  
Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Bonding Interface ◽  
Oxide Semiconductor ◽  
Mos Transistors ◽  
Germanium Nanocrystals ◽  
Germanium Layer

The properties of germanium implanted into the SiO2 layers in the vicinity of the bonding interface of silicon-on-insulator (SOI) structures are studied. It is shown that no germanium nanocrystals are formed in the buried SiO2 layer of the SOI structure as a result of annealing at the temperature of 1100° C. The implanted Ge atoms segregate at the Si/SiO2 bonding interface. In this case, Ge atoms are found at sites that are coherent with the lattice of the top silicon layer. It is found that the slope of the drain–gate characteristics of the back metal-oxide-semiconductor (MOS) transistors, prepared in the Ge+ ion implanted structures, increases. This effect is attributed to the grown hole mobility due to the contribution of an intermediate germanium layer formed at the Si/SiO2 interface.

A Study of Melting and Resolidification of Silicon-on-Insulator Structures Formed by Lateral Epitaxy

1985 ◽  
Vol 53 ◽  
Author(s):  
D A Williams ◽  
R A Mcmahon ◽  
D G Hasko ◽  
H Ahmed ◽  
G F Hopper ◽  
...  
Keyword(s):  
Cross Sections ◽  
Silicon On Insulator ◽  
One Dimensional ◽  
Wide Range ◽  
Background Temperature ◽  
Lateral Epitaxy ◽  
Polycrystalline Silicon Films ◽  
Beam Technique ◽  
Sweep Speed

ABSTRACTThe formation of silicon-on-insulator structures, by recrystallising polycrystalline silicon films with a dual electron beam technique, has been studied over a wide range of conditions. The quality of the layers has been assessed by examining cross-sections in the SEM and optical microscopy of the surface after a Secco etch. The range of line powers which gives device-worthy single crystal material becomes greater as the sweep speed increases and as the background temperature is reduced. The extent of melting into the substrate in the seed windows and below the isolating oxide was determined from the movement of an arsenic implant. The experimental results are compared to the predictions from a one dimensional model for the heat flow.

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