Reduction of reverse leakage current at the TiO2/GaN interface in field plate Ni/Au/n-GaN Schottky diodes

This paper presents the fabrication procedure of TiO2 passivated field plate Schottky diode and gives a comparison of Ni/Au/n-GaN Schottky barrier diodes without field plate and with field plate of varying diameters from 50 to 300 µm. The influence of field oxide (TiO2) on the leakage current of Ni/Au/n-GaN Schottky diode was investigated. This suggests that the TiO2 passivated structure reduces the reverse leakage current of Ni/Au/n-GaN Schottky diode. Also, the reverse leakage current of Ni/Au/n-GaN Schottky diodes decreases as the field plate length increases. The temperature-dependent electrical characteristics of TiO2 passivated field plate Ni/Au/n-GaN Schottky diodes have shown an increase of barrier height within the temperature range 300…475 K.

Comparison of Different Ways of Extra Phosphorus Implantation Which Decrease the Threshold Voltage and On-resistance of UMOS

A method to decrease the threshold voltage and on-resistance is discussed in this paper, which is adding extra phosphorus implantation into silicon. There are two ways to implant extra phosphorus without adding a mask. The first way is to implant extra phosphorus after the field oxide etching, and the second way is to implant extra phosphorus with the source region mask before the N+ implantation. Compare the results of the two ways to find their characteristics and choose the appropriate one.

Effect of the Field Oxidation Process on the Electrical Characteristics of 6500V 4H-SiC JBS Diodes

The effect of the field oxidation process on the electrical characteristics of 6500V 4H-SiC JBS diodes is studied. The oxide thickness and field plate length have an effect on the reverse breakdown voltage of the SiC JBS diode. According the simulation results, we choose the optimal thickness of the oxide layer and field plate length of the SiC JBS diode. Two different field oxide deposition processes, which are plasma enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD), are compared in our paper. When the reverse voltage is 6600V, the reverse leakage current of SiC JBS diodes with the field oxide layer obtained by LPCVD process is 0.7 μA, which is 60% lower than that of PECVD process. When the forward current is 25 A, the forward voltage of SiC JBS diodes with the field oxide layer obtained by LPCVD process is 3.75 V, which is 10% higher than that of PECVD process. There should be a trade-off between the forward and reverse characteristics in the actual high power and high temperature applications.

Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

Electrostatic discharge (ESD) events are the main factors impacting the reliability of Integrated circuits (ICs); therefore, the ESD immunity level of these ICs is an important index. This paper focuses on comprehensive drift-region engineering for ultra-high-voltage (UHV) circular n-channel lateral diffusion metal-oxide-semiconductor transistor (nLDMOS) devices used to investigate impacts on ESD ability. Under the condition of fixed layout area, there are four kinds of modulation in the drift region. First, by floating a polysilicon stripe above the drift region, the breakdown voltage and secondary breakdown current of this modulation can be increased. Second, adjusting the width of the field-oxide layer in the drift region when the width of the field-oxide layer is 5.8 μm will result in the minimum breakdown voltage (105 V) but the best secondary breakdown current (6.84 A). Third, by adjusting the discrete unit cell and its spacing, the corresponding improved trigger voltage, holding voltage, and secondary breakdown current can be obtained. According to the experimental results, the holding voltage of all devices under test (DUTs) is greater than that of the reference group, so the discrete HV N-Well (HVNW) layer can effectively improve its latch-up immunity. Finally, by embedding different P-Well lengths, the findings suggest that when the embedded P-Well length is 9 μm, it will have the highest ESD ability and latch-up immunity.