scholarly journals High-Drain Field Impacting Channel-Length Modulation Effect for Nano-Node N-Channel FinFETs

Crystals ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 262
Author(s):  
Mu-Chun Wang ◽  
Wen-Ching Hsieh ◽  
Chii-Ruey Lin ◽  
Wei-Lun Chu ◽  
Wen-Shiang Liao ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Gate Oxide ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Modulation Effect ◽  
Short Channel ◽  
Horizontal Drain ◽  
Source Voltage ◽  
Drain Field ◽  
28 Nm

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate voltage (VGS-VT) and the higher drain/source voltage VDS, the channel-length modulation (CLM) effect coming from the interaction impact of vertical gate field and horizontal drain field was increased and had to be revised well as the channel length L was decreased. Compared to the 28-nm MOSFETs, the interaction effect from the previous at the tested FinFETs on SOI substrate with the short-channel length L is lower than that at the 28-nm device, which means the interaction severity of both fields for nFinFETs is mitigated, but still necessary to be concerned.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

2018 ◽  
Vol 32 (15) ◽  
pp. 1850157 ◽  
Author(s):  
Yue-Gie Liaw ◽  
Chii-Wen Chen ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Xuecheng Zou
Keyword(s):  
Gate Oxide ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Current Crowding ◽  
Crowding Effect ◽  
Short Channel ◽  
Channel Mobility ◽  
Channel Effect ◽  
193 Nm ◽  
Dry Etch

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.

Modeling and Designing a Device Using MuGFETs

2008 ◽  
Author(s):  
V. K. Lamba ◽  
Derick Engles ◽  
S. S. Malik
Keyword(s):  
Gate Dielectric ◽  
Silicon Film ◽  
General Rule ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Radius Of Curvature ◽  
Short Channel ◽  
Dielectric Thickness ◽  
Fin Thickness

This work describes computer simulations of various, Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) with double and triple-gate structures, as well as gate-all-around devices. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. Here short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as Drain induced barrier lowering (DIBL), sub-threshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.

scholarly journals Analysis of Low Dimensional Nanoscaled Inversion-Mode InGaAs MOSFETs for Next-Generation Electrical and Photonic Applications

2015 ◽  
Vol 2015 ◽  
pp. 1-6
Author(s):  
C. H. Yu ◽  
X. Y. Chen ◽  
X. D. Luo ◽  
W. W. Xu ◽  
P. S. Liu
Keyword(s):  
Leakage Current ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Length ◽  
Next Generation ◽  
Short Channel ◽  
Channel Effects ◽  
Operating Limits ◽  
Low Dimensional ◽  
Interface Passivation

The electrical characteristics of In0.53Ga0.47As MOSFET grown with Si interface passivation layer (IPL) and highkgate oxide HfO2layer have been investigated in detail. The influences of Si IPL thickness, gate oxide HfO2thickness, the doping depth, and concentration of source and drain layer on output and transfer characteristics of the MOSFET at fixed gate or drain voltages have been individually simulated and analyzed. The determination of the above parameters is suggested based on their effect on maximum drain current, leakage current, saturated voltage, and so forth. It is found that the channel length decreases with the increase of the maximum drain current and leakage current simultaneously. Short channel effects start to appear when the channel length is less than 0.9 μm and experience sudden sharp increases which make device performance degrade and reach their operating limits when the channel length is further lessened down to 0.5 μm. The results demonstrate the usefulness of short channel simulations for designs and optimization of next-generation electrical and photonic devices.

A Seeded Channel Approach to Silicon-On-Insulator Technology

1985 ◽  
Vol 53 ◽  
Author(s):  
C. H. Ting ◽  
W. Baerg ◽  
H. Y. Lin ◽  
B. Siu ◽  
T. Hwa ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Channel Length ◽  
Crystalline Material ◽  
Silicon On Insulator ◽  
Thin Film Thickness ◽  
Laser Recrystallization ◽  
Computer Controlled ◽  
Channel Region ◽  
Standard Production ◽  
The Ideal

ABSTRACTA seeded channel approach was developed to avoid the short comings of the conventional SOI structure such as grain or sub-grain boundaries in the channel region, floating substrate effects, etc. In this approach, the gate of each FET is located above its own seed window to insure that single crystalline material is obtained for the channel region. The source and drain regions, however, are located in the recrystallized silicon over Si02 for improved isolation and minimizing junction capacitance. Recrystallization was obtained in 4" silicon wafers by using an Ar laser and a computer controlled X-Y stage with heated substrate holder. Problems encountered in laser recrystallization, such as, reflectivity variations over seed and SOI regions, surface ripples, pittings, etc., were eliminated by optimizing the thin film thickness of the isolation oxide, polysilicon, and the capping oxide. This technology was used successfully to fabricate FET devices using a standard production n-MOS process. Good device characteristics were obtainred using 400Å gate oxide and channel length ranging from 1um to 50um. The measured electron mobility in the channel region is, however still lower than the ideal bulk values.

scholarly journals Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET

2019 ◽  
Vol 9 (1) ◽  
pp. 163
Author(s):  
Hakkee Jung
Keyword(s):  
Threshold Voltage ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Double Gate ◽  
Short Channel ◽  
Double Gate Mosfet ◽  
Channel Effects ◽  
Channel Thickness

Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET

2017 ◽  
Vol 27 (04) ◽  
pp. 1850063 ◽  
Author(s):  
Rajneesh Sharma ◽  
Rituraj S. Rathore ◽  
Ashwani K. Rana
Keyword(s):  
Dielectric Materials ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Effects ◽  
The Impact ◽  
Gate Underlap

The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ([Formula: see text]). However, the gate underlap also results in reduced ON current ([Formula: see text]) due to increased effective channel length. The use of high-[Formula: see text] material as a spacer region helps to achieve the higher [Formula: see text] but at the cost of increased effective gate capacitance ([Formula: see text]) which degrades the device performance. Thus, the impact of high-[Formula: see text] spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]/[Formula: see text] ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the [Formula: see text]/[Formula: see text] ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO2 of 10[Formula: see text]nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in [Formula: see text] especially below 20[Formula: see text]nm gate length.

scholarly journals Parameter Analysis of CNTFET

2019 ◽  
Vol 8 (2) ◽  
pp. 5355-5359
Keyword(s):  
Dielectric Constant ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Parameter Analysis ◽  
Source Voltage

In this paper, a parameter analysis of CNTFET is presented with different parameters variations such as gate to source voltage vgs, oxide thickness tox, gate oxide dielectric Kox, channel length L, source/drain spacer dielectric constant Kspa ect. All the parameters of CNTFET have been varied in CADENCE Virtuoso environment and verified with the preferred value of stanford VS-CNTFET model

scholarly journals An analytical subthreshold current/swing model for junctionless cylindrical nanowire FETs (JLCNFETs)

2013 ◽  
Vol 26 (3) ◽  
pp. 157-173 ◽  
Author(s):  
Te-Kuang Chiang ◽  
Juin Liou
Keyword(s):  
Electron Density ◽  
Silicon Film ◽  
Three Dimensional ◽  
Oxide Thickness ◽  
Channel Length ◽  
Short Channel ◽  
Doping Density ◽  
Factor B ◽  
Subthreshold Current ◽  
Channel Effects

Based on the parabolic potential approach (PPA), scaling theory, and drift-diffusion approach (DDA) with effective band gap widening (BGW), we propose an analytical subthreshold current/swing model for junctionless (JL) cylindrical nanowire FETs (JLCNFETs). The work indicates that the electron density of Qm that is induced by the current factor b, minimum central potential Fc, min and equivalent quantum potential FQM is used to determine the subthreshold current/swing for JLCNFET. Unlike the junction-based (JB) cylindrical nanowire FETs (JBCNFETs), the subthreshold current for JLCNFET is not linearly proportional to the silicon diameter, but linearly proportional to the current factor b due to the depletion-typed operation. Apart from short-channel effects (SCEs), the quantum-mechanics effects (QMEs) are included in the model by accounting for the effective BGW, which decreases the electron density in the subthreshold regime and reduces the subthreshold current consequently. Band-to-band tunneling (BTBT) that impacts the subthreshold current is also discussed in the end of the paper. The model explicitly shows how the bulk doping density, drain bias, channel length, oxide thickness, gate workfunction, and silicon film diameter affect the subthreshold current/swing. The model is verified by its calculated results matching well with the data simulated from the three-dimensional device simulator and can be used to investigate the subthreshold current/swing for JLCNFET.

The Effect of Roughness Features on Mos Surface Electric Field and Fowler-Nordheim Tunneling Behavior

1997 ◽  
Vol 473 ◽  
Author(s):  
Heng-Chih Lin ◽  
Edwin C. Kan ◽  
Toshiaki Yamanaka ◽  
Simon J. Fang ◽  
Kwame N. Eason ◽  
...  
Keyword(s):  
Electric Field ◽  
Three Dimensional ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Interface Roughness ◽  
Normal Electric Field ◽  
Surface Electric Field ◽  
Tunneling Behavior ◽  
Nordheim Tunneling

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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