Design of a Capacitorless Dynamic Random Access Memory Based on Junctionless Dual-Gate Field-Effect Transistor with a Silicon-Germanium/Silicon Nanotube

In this paper, a 1T-DRAM based on the junctionless field-effect transistor (JLFET) with a silicon-germanium (SiGe) and silicon (Si) nanotube structure was designed and investigated by using technology computer-aided design (TCAD) simulations. Utilizing bandgap engineering to make a quantum well in the core–shell structure, the storage pocket is formed by the difference in bandgap energy between SiGe and Si. By applying different voltage conditions at the inner gate and outer gate, excess holes are generated in the storage region by the band-to-band tunneling (BTBT) mechanism. The BTBT mechanism results in the floating body effect, which is the principle of 1T-DRAM. The varying amount of the accumulated holes in the SiGe region allows differentiating between state “1” and state “0.” Additionally, the outer gate plays a role of the conventional gate, while the inner gate retains holes in the hold state by applying voltage. Consequently, the optimized SiGe/Si JLFET-based nanotube 1T-DRAM achieved a high sensing margin of 15.4 μA/μm, and a high retention time of 105 ms at a high temperature of 358 K. In addition, it has been verified that a single cycle of 1T-DRAM operations consumes only 33.6 fJ of energy, which is smaller than for previously proposed 1T-DRAMs.

Dynamics, Design, and Application of a Silicon-on-Insulator Technology Based Neuron

Spiking Neural Networks propose to mimic nature’s way of recognizing patterns and making decisions in a fuzzy manner. To develop such networks in hardware, a highly manufacturable technology is required. We have proposed a silicon-based leaky integrate and fire (LIF) neuron, on a sufficiently matured 32 nm CMOS silicon-on-insulator (SOI) technology. The floating body effect of the partially depleted (PD) SOI transistor is used to store “holes” generated by impact ionization in the floating body, which performs the “integrate” function. Recombination or equivalent hole loss mimics the “leak” functions. The “hole” storage reduces the source barrier to increase the transistor current. Upon reaching a threshold current level, an external circuit records a “firing” event and resets the SOI MOSFET by draining all the stored holes. In terms of application, the neuron is able to show classification problems with reasonable accuracy. We looked at the effect of scaling experimentally. Channel length scaling reduces voltage for impact ionization and enables sharper impact ionization producing significant designability of the neuron. A circuit equivalence is also demonstrated to understand the dynamics qualitatively. Three distinct regimes are observed during integration based on different hole leakage mechanism.