Gate-oxide integrity of silicon-on-insulator transistors

1987 ◽  
Vol 23 (4) ◽  
pp. 175 ◽  
Author(s):  
T.I. Kamins
Keyword(s):  
Gate Oxide ◽  
Silicon On Insulator ◽  
Gate Oxide Integrity

Solutions to Gate Oxide Integrity on TFSOI Substrates Caused by PMOS Threshold-Voltage Implant

1998 ◽  
Vol 510 ◽  
Author(s):  
S. Q. Hong ◽  
T. Wetteroth ◽  
S. R. Wilson ◽  
B. Steele ◽  
D. K. Schroder
Keyword(s):  
Threshold Voltage ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Oxide Growth ◽  
Oxide Breakdown ◽  
Oxide Degradation ◽  
Process Damage ◽  
Gate Oxide Integrity

AbstractDue to the lack of effective gettering, gate oxide on thin-film-silicon-on-insulator (TFSOI) substrates is much more sensitive than its bulk Si counterpart to process damage during device fabrication, especially prior to gate oxide growth. Presented in this paper as a typical example is the severe oxide degradation caused by PMOS threshold-voltage implant. Several approaches to circumvent this problem are explored, such as Vt implant without sacrificial oxide (sacox), low temperature anneal before sacox removal, or implementation of lateral gettering. As a result of these efforts, a significant improvement in gate oxide integrity is achieved with increased oxide breakdown voltages and charge-to-breakdowns, as well as a reduction in oxide charge trapping. This work also demonstrates the feasibility of achieving bulk-comparable gate oxide on TFSOI substrates.

Improvement in gate oxide integrity on thin-film silicon-on-insulator substrates by lateral gettering

1997 ◽  
Vol 71 (23) ◽  
pp. 3397-3399 ◽  
Author(s):  
S. Q. Hong ◽  
T. Wetteroth ◽  
H. Shin ◽  
S. R. Wilson ◽  
D. Werho ◽  
...  
Keyword(s):  
Thin Film ◽  
Gate Oxide ◽  
Silicon On Insulator ◽  
Thin Film Silicon ◽  
Gate Oxide Integrity

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Materials, device and gate oxide integrity evaluation of SIMOX and bonded SOI wafers

2002 ◽  
Author(s):  
S.R. Wilson ◽  
T. Wetteroth ◽  
S. Hong ◽  
H. Shin ◽  
B.-Y. Hwang ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Gate Oxide Integrity

Gate oxide integrity on ITOX-SIMOX substrates and influence of test device geometry on characterization

2001 ◽  
Vol 48 (2) ◽  
pp. 307-315 ◽  
Author(s):  
K. Kawamura ◽  
H. Deai ◽  
H. Sakamoto ◽  
T. Yano ◽  
I. Hamaguchi ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Test Device ◽  
Device Geometry ◽  
Gate Oxide Integrity

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

2018 ◽  
Vol 32 (15) ◽  
pp. 1850157 ◽  
Author(s):  
Yue-Gie Liaw ◽  
Chii-Wen Chen ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Xuecheng Zou
Keyword(s):  
Gate Oxide ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Current Crowding ◽  
Crowding Effect ◽  
Short Channel ◽  
Channel Mobility ◽  
Channel Effect ◽  
193 Nm ◽  
Dry Etch

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.

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