Carbon Doped Silicon Emitters Fabricated Using Limited Reaction Processing

1990 ◽  
Vol 198 ◽  
Author(s):  
F.H. Ruddell ◽  
B.M. Armstrong ◽  
H.S. Gamble ◽  
K.B. Affolter ◽  
P.B. Moynagh ◽  
...  
Keyword(s):  
Deposition Process ◽  
Bipolar Transistors ◽  
Tem Analysis ◽  
Thermal Budget ◽  
Carbon Doped ◽  
Analysis Techniques ◽  
Doped Silicon ◽  
Low Thermal Budget ◽  
Reaction Processing

ABSTRACTThis paper describes the deposition of in-situ doped N-type silicon carbide layers in a Limited Reaction Processing (LRP) reactor. Silane/propane/ phosphine gas chemistry was used at temperatures less than 1000°C and SIMS, XPS and TEM analysis techniques aided layer characterisation. A low thermal budget deposition process (1 min at 970°C) was employed to form the emitters of Sic/Si heterojunction NPN bipolar transistors. These devices yielded a factor of two increase in emitter Gummel number compared to diffused emitters.

Polysilicon Emitter Transistors Manufactured using a Novel Limited Reaction Processing System

1989 ◽  
Vol 146 ◽  
Author(s):  
Fred Ruddell ◽  
Colin Parkes ◽  
B Mervyn Armstrong ◽  
Harold S Gamble
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Processing System ◽  
Bipolar Transistors ◽  
Native Oxide ◽  
Plasma Oxidation ◽  
Oxide Removal ◽  
Polysilicon Emitter ◽  
Reaction Processing

ABSTRACTThis paper describes a LPCVD reactor which was developed for multiple sequential in-situ processing. The system is capable of rapid thermal processing in the presence of plasma stimulation and has been used for native oxide removal, plasma oxidation and silicon deposition. Polysilicon layers produced by the system are incorporated into N-P-N polysilicon emitter bipolar transistors. These devices fabricated using a sequential in-situ plasma clean-polysilicon deposition schedule exhibited uniform gains limited to that of long single crystal emitters. Devices with either plasma grown or native oxide layers below the polysilicon exhibited much higher gains. The suitability of the system for sequential and limited reaction processing has been established.

A Low‐Thermal‐Budget In Situ Doped Multilayer Silicon Epitaxy Process for MOSFET Channel Engineering

1999 ◽  
Vol 146 (3) ◽  
pp. 1189-1196 ◽  
Author(s):  
Ibrahim Ban ◽  
Mehmet C. Öztürk ◽  
Veena Misra ◽  
Jimmie J. Wortman ◽  
Dave Venables ◽  
...  
Keyword(s):  
Thermal Budget ◽  
Silicon Epitaxy ◽  
Channel Engineering ◽  
Low Thermal Budget
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