In situ arsenic‐doped polycrystalline silicon as a low thermal budget emitter contact for Si/Si1−xGex heterojunction bipolar transistors

1996 ◽  
Vol 68 (2) ◽  
pp. 226-228 ◽  
Author(s):  
C. A. King ◽  
R. W. Johnson ◽  
M. R. Pinto ◽  
H. S. Luftman ◽  
J. Munanka
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Polycrystalline Silicon ◽  
Bipolar Transistors ◽  
Thermal Budget ◽  
Low Thermal Budget

Carbon Doped Silicon Emitters Fabricated Using Limited Reaction Processing

1990 ◽  
Vol 198 ◽  
Author(s):  
F.H. Ruddell ◽  
B.M. Armstrong ◽  
H.S. Gamble ◽  
K.B. Affolter ◽  
P.B. Moynagh ◽  
...  
Keyword(s):  
Deposition Process ◽  
Bipolar Transistors ◽  
Tem Analysis ◽  
Thermal Budget ◽  
Carbon Doped ◽  
Analysis Techniques ◽  
Doped Silicon ◽  
Low Thermal Budget ◽  
Reaction Processing

ABSTRACTThis paper describes the deposition of in-situ doped N-type silicon carbide layers in a Limited Reaction Processing (LRP) reactor. Silane/propane/ phosphine gas chemistry was used at temperatures less than 1000°C and SIMS, XPS and TEM analysis techniques aided layer characterisation. A low thermal budget deposition process (1 min at 970°C) was employed to form the emitters of Sic/Si heterojunction NPN bipolar transistors. These devices yielded a factor of two increase in emitter Gummel number compared to diffused emitters.

scholarly journals Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors

1996 ◽  
Vol 17 (11) ◽  
pp. 503-505 ◽  
Author(s):  
Hsiao-Yi Lin ◽  
Chun-Yen Chang ◽  
Tan Fu Lei ◽  
Feng-Ming Liu ◽  
Wen-Luh Yang ◽  
...  
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Silicon Thin Film ◽  
Thermal Budget ◽  
Low Thermal Budget

A Low‐Thermal‐Budget In Situ Doped Multilayer Silicon Epitaxy Process for MOSFET Channel Engineering

1999 ◽  
Vol 146 (3) ◽  
pp. 1189-1196 ◽  
Author(s):  
Ibrahim Ban ◽  
Mehmet C. Öztürk ◽  
Veena Misra ◽  
Jimmie J. Wortman ◽  
Dave Venables ◽  
...  
Keyword(s):  
Thermal Budget ◽  
Silicon Epitaxy ◽  
Channel Engineering ◽  
Low Thermal Budget

Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing

2017 ◽  
Vol 10 (2) ◽  
pp. 026502 ◽  
Author(s):  
Wen-Hsien Huang ◽  
Jia-Min Shieh ◽  
Ming-Hsuan Kao ◽  
Chang-Hong Shen ◽  
Tzu-En Huang ◽  
...  
Keyword(s):  
Laser Annealing ◽  
Pulsed Laser ◽  
Thermal Budget ◽  
Pulsed Laser Annealing ◽  
Low Thermal Budget
Sign in / Sign up

Export Citation Format

Share Document