scholarly journals Impact of ex-situ and in-situ cleans on the performance of bipolar transistors with low thermal budget in-situ phosphorus-doped polysilicon emitter contacts

2001 ◽  
Vol 48 (11) ◽  
pp. 2506-2513 ◽  
Author(s):  
A.I.A. Rahim ◽  
C.D. Marsh ◽  
P. Ashburn ◽  
G.R. Booker
Keyword(s):  
Bipolar Transistors ◽  
Ex Situ ◽  
Thermal Budget ◽  
Low Thermal Budget ◽  
Polysilicon Emitter ◽  
Phosphorus Doped

Carbon Doped Silicon Emitters Fabricated Using Limited Reaction Processing

1990 ◽  
Vol 198 ◽  
Author(s):  
F.H. Ruddell ◽  
B.M. Armstrong ◽  
H.S. Gamble ◽  
K.B. Affolter ◽  
P.B. Moynagh ◽  
...  
Keyword(s):  
Deposition Process ◽  
Bipolar Transistors ◽  
Tem Analysis ◽  
Thermal Budget ◽  
Carbon Doped ◽  
Analysis Techniques ◽  
Doped Silicon ◽  
Low Thermal Budget ◽  
Reaction Processing

ABSTRACTThis paper describes the deposition of in-situ doped N-type silicon carbide layers in a Limited Reaction Processing (LRP) reactor. Silane/propane/ phosphine gas chemistry was used at temperatures less than 1000°C and SIMS, XPS and TEM analysis techniques aided layer characterisation. A low thermal budget deposition process (1 min at 970°C) was employed to form the emitters of Sic/Si heterojunction NPN bipolar transistors. These devices yielded a factor of two increase in emitter Gummel number compared to diffused emitters.

Effect of rapid epitaxy in in situ phosphorus-doped polysilicon emitter on current-gain of bipolar transistors

1996 ◽  
Vol 43 (8) ◽  
pp. 1281-1285 ◽  
Author(s):  
T. Shiba ◽  
M. Kondo ◽  
T. Uchino ◽  
H. Murakoshi ◽  
Y. Tamaki
Keyword(s):  
Bipolar Transistors ◽  
Current Gain ◽  
Polysilicon Emitter ◽  
Phosphorus Doped

Control of Polysilicon Emitter Bipolar Transistor Characteristics by Rapid Thermal or Furnace Anneal of the Polysilicon/Silicon Interface

1992 ◽  
Vol 283 ◽  
Author(s):  
S. Bhattacharya ◽  
M. Lobo ◽  
L. Jung ◽  
S. Banerjee ◽  
R. Reuss ◽  
...  
Keyword(s):  
Chemical Vapor ◽  
Oxide Thickness ◽  
Bipolar Transistors ◽  
Ex Situ ◽  
Current Gain ◽  
Pressure Chemical ◽  
Break Up ◽  
Polysilicon Emitter ◽  
Silicon Interface

ABSTRACTIn this paper we report on the ability of rapid thermal annealing (1050C, 45s) and furnace annealing (900C, 30min) to partially break up the interfacial oxide in bipolar transistors with different oxide thicknesses at the polysilicon/silicon interface. We have obtained the different oxide thicknesses either by performing different ex situ cleans (RCA clean or RCA clean + HF dip) before Low Pressure Chemical Vapor Deposition (LPCVD) of polysilicon, or by using a cluster tool for polysilicon deposition with the ability to perform an in situ clean and then allowing the growth of different oxide thicknesses at the interface prior to polysilicon deposition. For the in situ cleaned devices, it is observed that after the interface anneal, the current gain increases with increasing oxide thicknesses, but with little penalty in terms of higher emitter resistance, Re. This indicates that by controllably increasing the interfacial oxide thickness and by subsequent annealing to partially break up the interfacial oxide, higher current gains can be obtained with little sacrifice in terms of higher Re.

Polysilicon Emitter Transistors Manufactured using a Novel Limited Reaction Processing System

1989 ◽  
Vol 146 ◽  
Author(s):  
Fred Ruddell ◽  
Colin Parkes ◽  
B Mervyn Armstrong ◽  
Harold S Gamble
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Processing System ◽  
Bipolar Transistors ◽  
Native Oxide ◽  
Plasma Oxidation ◽  
Oxide Removal ◽  
Polysilicon Emitter ◽  
Reaction Processing

ABSTRACTThis paper describes a LPCVD reactor which was developed for multiple sequential in-situ processing. The system is capable of rapid thermal processing in the presence of plasma stimulation and has been used for native oxide removal, plasma oxidation and silicon deposition. Polysilicon layers produced by the system are incorporated into N-P-N polysilicon emitter bipolar transistors. These devices fabricated using a sequential in-situ plasma clean-polysilicon deposition schedule exhibited uniform gains limited to that of long single crystal emitters. Devices with either plasma grown or native oxide layers below the polysilicon exhibited much higher gains. The suitability of the system for sequential and limited reaction processing has been established.

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