Process Challenges for Integration of Copper Interconnects with Low-k Dielectrics

2019 ◽  
Vol 35 (4) ◽  
pp. 687-699 ◽  
Author(s):  
Jeff Gambino
Keyword(s):  
Copper Interconnects ◽  
Low K

Failure Modes, Reliability Analysis and Case Studies on the Integration of Copper and Low-K Technology

2004 ◽  
Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Huixian Wu ◽  
Marvin White
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Copper Interconnects ◽  
Wet Chemical ◽  
Low K ◽  
Section Analysis

Abstract The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.

Via Cleaning Technology for Post Etch Residues

2005 ◽  
Vol 103-104 ◽  
pp. 357-360
Author(s):  
B.G. Sharma ◽  
Chris Prindle
Keyword(s):  
Semiconductor Industry ◽  
Dielectric Materials ◽  
Copper Interconnects ◽  
Limiting Factor ◽  
Device Performance ◽  
Semiconductor Technology ◽  
Widespread Acceptance ◽  
Cleaning Technology ◽  
Rc Delay ◽  
Low K

Interconnect RC delay is the limiting factor for device performance in submicron semiconductor technology. Copper and low-k dielectric materials can reduce this delay and have gained widespread acceptance in the semiconductor industry. The presence of copper interconnects provides unprecedented challenges for via cleaning technology and requires the development of novel process chemistries for improved device capability.

Improvement on Intrinsic Electrical Properties of Low-k Hydrogen Silsesquioxane/Copper Interconnects Employing Deuterium Plasma Treatment

2000 ◽  
Vol 147 (3) ◽  
pp. 1186 ◽  
Author(s):  
Po-Tsun Liu ◽  
Ting-Chang Chang ◽  
Ya-Liang Yang ◽  
Yi-Fang Cheng ◽  
Jae-Kyun Lee ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Plasma Treatment ◽  
Copper Interconnects ◽  
Deuterium Plasma ◽  
Hydrogen Silsesquioxane ◽  
Low K

Diffusion Barriers For Fluorinated Low-k Dielectrics

1999 ◽  
Vol 565 ◽  
Author(s):  
M. DelaRosa ◽  
A. Kumar ◽  
H. Bakhru ◽  
T.-M. Lu
Keyword(s):  
Barrier Layer ◽  
Process Integration ◽  
Diffusion Barriers ◽  
Copper Interconnects ◽  
Nuclear Reaction Analysis ◽  
Fluorine Concentration ◽  
Dielectric Barrier ◽  
Barrier Materials ◽  
Teflon Af ◽  
Low K

AbstractThe fluorinated low-k dielectrics SiO:F and Teflon AF were investigated for process integration with aluminum and copper interconnects. To minimize fluorine diffusion, several potential barrier materials were deposited onto the fluorinated dielectrics and characterized after heat treatment at temperatures up to 450°C. The barrier layers studied include conventional materials such as Ta, TaN, and TiN, in addition to several novel materials. Barrier layer materials were deposited using evaporation, and sputtering. The materials were characterized using nuclear reaction analysis (NRA) to determine the fluorine concentration profile. A reaction zone was noted at the dielectric-barrier interface on several samples, corresponding to the formation of a fluoride complex. In some instances, this fluoride layer was self-limiting and prevented further fluorine diffusion through the remainder of the barrier layer.

scholarly journals Physics-Based Compact TDDB Models for Low- $k$ BEOL Copper Interconnects With Time-Varying Voltage Stressing

2018 ◽  
Vol 26 (2) ◽  
pp. 239-248 ◽  
Author(s):  
Shaoyi Peng ◽  
Han Zhou ◽  
Taeyoung Kim ◽  
Hai-Bao Chen ◽  
Sheldon X.-D. Tan
Keyword(s):  
Copper Interconnects ◽  
Time Varying ◽  
Low K

Automated Sample Preparation of Low-k Dielectrics for FESEM

2005 ◽  
Author(s):  
R. R. Cerchiara ◽  
H. A. Cook ◽  
P. E. Fischione ◽  
J. J. Gronsky ◽  
J. M. Matesa ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Ion Beam ◽  
Reactive Ion Etching ◽  
Copper Interconnects ◽  
Plasma Cleaning ◽  
Ion Etching ◽  
Ion Beam Etching ◽  
Automated Sample Preparation ◽  
Microelectronic Materials ◽  
Low K

Abstract The SiLK resins, composed of aromatic hydrocarbons, are a family of highly cross-linked thermoset polymers with isotropic dielectric properties. Patterning of SiLK for high aspect ratio copper interconnects has depended on reactive ion etching with oxygen/nitrogen gas mixtures. Reactive ion etching is therefore also accomplished with reducing plasmas such as nitrogen/hydrogen. An additional plasma cleaning step can be inserted after the reactive ion etching (RIE) step, so that any residual contamination is removed prior to imaging or final sputter coating. Automated sample preparation of microelectronic materials containing high and low-k dielectrics for FESEM is accomplished in this article by combining these techniques: plasma cleaning, ion beam etching, and reactive ion etching. A single RIE chemistry was effective in etching both dielectrics as well as delineating the other phases present.

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