Diffusion Barriers For Fluorinated Low-k Dielectrics

1999 ◽  
Vol 565 ◽  
Author(s):  
M. DelaRosa ◽  
A. Kumar ◽  
H. Bakhru ◽  
T.-M. Lu
Keyword(s):  
Barrier Layer ◽  
Process Integration ◽  
Diffusion Barriers ◽  
Copper Interconnects ◽  
Nuclear Reaction Analysis ◽  
Fluorine Concentration ◽  
Dielectric Barrier ◽  
Barrier Materials ◽  
Teflon Af ◽  
Low K

AbstractThe fluorinated low-k dielectrics SiO:F and Teflon AF were investigated for process integration with aluminum and copper interconnects. To minimize fluorine diffusion, several potential barrier materials were deposited onto the fluorinated dielectrics and characterized after heat treatment at temperatures up to 450°C. The barrier layers studied include conventional materials such as Ta, TaN, and TiN, in addition to several novel materials. Barrier layer materials were deposited using evaporation, and sputtering. The materials were characterized using nuclear reaction analysis (NRA) to determine the fluorine concentration profile. A reaction zone was noted at the dielectric-barrier interface on several samples, corresponding to the formation of a fluoride complex. In some instances, this fluoride layer was self-limiting and prevented further fluorine diffusion through the remainder of the barrier layer.

Diffusion Barriers for Fluorinated Low-k Dielectrics

1999 ◽  
Vol 564 ◽  
Author(s):  
M. DelaRosa ◽  
A. Kumar ◽  
H. Bakhru ◽  
T.-M. Lu
Keyword(s):  
Barrier Layer ◽  
Process Integration ◽  
Diffusion Barriers ◽  
Copper Interconnects ◽  
Nuclear Reaction Analysis ◽  
Fluorine Concentration ◽  
Dielectric Barrier ◽  
Barrier Materials ◽  
Teflon Af ◽  
Low K

AbstractThe fluorinated low-k dielectrics SiO:F and Teflon AF were investigated for process integration with aluminum and copper interconnects. To minimize fluorine diffusion, several potential barrier materials were deposited onto the fluorinated dielectrics and characterized after heat treatment at temperatures up to 450°C. The barrier layers studied include conventional materials such as Ta, TaN, and TiN, in addition to several novel materials. Barrier layer materials were deposited using evaporation, and sputtering. The materials were characterized using nuclear reaction analysis (NRA) to determine the fluorine concentration profile. A reaction zone was noted at the dielectric-barrier interface on several samples, corresponding to the formation of a fluoride complex. hI some instances, this fluoride layer was self-limiting and prevented further fluorine diffusion through the remainder of the barrier layer.

Ion Beam Techniques for Low K Materials Characterization

1998 ◽  
Vol 511 ◽  
Author(s):  
H. Bakhru ◽  
A. Kumar ◽  
T. Kaplan ◽  
M. Delarosa ◽  
J. Fortin ◽  
...  
Keyword(s):  
Rutherford Backscattering Spectrometry ◽  
Ion Beam ◽  
Nuclear Reaction Analysis ◽  
Ion Beam Analysis ◽  
Analytical Technique ◽  
Analysis Techniques ◽  
Teflon Af ◽  
Beam Analysis ◽  
Low K

ABSTRACTIon beam analysis techniques have become very useful for characterization of low k materials. Studies on several ion beam analysis techniques will be discussed. Rutherford Backscattering Spectrometry (RBS) provides a very powerful analytical technique for the thickness and porosity measurements on porous Si0 2 films. Nuclear Reaction Analysis (NRA) techniques for hydrogen and fluorine profiling are very useful to characterize fluorinated polymer and fluorinated oxide films. Examples of low k materials including Si02:F, Parylene-AF and Teflon-AF will be discussed. Fluorine diffusion in to metals and various interface effects between metal and low k materials will be presented.

Failure Modes, Reliability Analysis and Case Studies on the Integration of Copper and Low-K Technology

2004 ◽  
Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Huixian Wu ◽  
Marvin White
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Copper Interconnects ◽  
Wet Chemical ◽  
Low K ◽  
Section Analysis

Abstract The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.

Effectiveness and Reliability of Metal Diffusion Barriers for Copper Interconnects

1995 ◽  
Vol 403 ◽  
Author(s):  
G. Bai ◽  
S. Wittenbrock ◽  
V. Ochoa ◽  
R. Villasol ◽  
C. Chiang ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Vapor Deposition ◽  
Physical Vapor Deposition ◽  
Chemical Vapor ◽  
Diffusion Barriers ◽  
Copper Interconnects ◽  
Time To Failure ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron

AbstractCu has two advantages over Al for sub-quarter micron interconnect application: (1) higher conductivity and (2) improved electromigration reliability. However, Cu diffuses quickly in SiO2and Si, and must be encapsulated. Polycrystalline films of Physical Vapor Deposition (PVD) Ta, W, Mo, TiN, and Metal-Organo Chemical Vapor Deposition (MOCVD) TiN and Ti-Si-N have been evaluated as Cu diffusion barriers using electrically biased-thermal-stressing tests. Barrier effectiveness of these thin films were correlated with their physical properties from Atomic Force Microscopy (AFM), Transmission Electron Microscopy (TEM), Secondary Electron Microscopy (SEM), and Auger Electron Spectroscopy (AES) analysis. The barrier failure is dominated by “micro-defects” in the barrier film that serve as easy pathways for Cu diffusion. An ideal barrier system should be free of such micro-defects (e.g., amorphous Ti-Si-N and annealed Ta). The median-time-to-failure (MTTF) of a Ta barrier (30 nm) has been measured at different bias electrical fields and stressing temperatures, and the extrapolated MTTF of such a barrier is > 100 year at an operating condition of 200C and 0.1 MV/cm.

Via Cleaning Technology for Post Etch Residues

2005 ◽  
Vol 103-104 ◽  
pp. 357-360
Author(s):  
B.G. Sharma ◽  
Chris Prindle
Keyword(s):  
Semiconductor Industry ◽  
Dielectric Materials ◽  
Copper Interconnects ◽  
Limiting Factor ◽  
Device Performance ◽  
Semiconductor Technology ◽  
Widespread Acceptance ◽  
Cleaning Technology ◽  
Rc Delay ◽  
Low K

Interconnect RC delay is the limiting factor for device performance in submicron semiconductor technology. Copper and low-k dielectric materials can reduce this delay and have gained widespread acceptance in the semiconductor industry. The presence of copper interconnects provides unprecedented challenges for via cleaning technology and requires the development of novel process chemistries for improved device capability.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

2015 ◽  
Vol 2015 (1) ◽  
pp. 000787-000792
Author(s):  
E. Misra ◽  
T. Wassick ◽  
I. Melville ◽  
K. Tunga ◽  
D. Questad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Lead Free ◽  
Solder Interconnects ◽  
Design Changes ◽  
Modeling Data ◽  
Free Solder ◽  
Low K

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

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