Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.
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114

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Wafer-level microfluidic cooling interconnects for GSI

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. ◽

10.1109/iitc.2005.1499971 ◽

2005 ◽

Cited By ~ 19

Author(s):

Bing Dang ◽

P. Joseph ◽

M. Bakir ◽

T. Spencer ◽

P. Kohl ◽

...

Keyword(s):

Wafer Level

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Low resistive and highly reliable Cu dual-damascene interconnect technology using self-formed MnSi/sub x/O/sub y/ barrier layer

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. ◽

10.1109/iitc.2005.1499975 ◽

2005 ◽

Cited By ~ 4

Author(s):

T. Usui ◽

H. Nasu ◽

J. Koike ◽

M. Wada ◽

S. Takahashi ◽

...

Keyword(s):

Barrier Layer ◽

Dual Damascene ◽

Interconnect Technology

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Copper-filled through wafer vias with very low inductance

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. ◽

10.1109/iitc.2005.1499957 ◽

2005 ◽

Cited By ~ 7

Author(s):

K.A. Jenkins ◽

C.S. Patel

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Using a low-k material with k=2.5 formed by a novel quasi-porogen approach for 65 nm Cu/LK interconnects

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. ◽

10.1109/iitc.2005.1499920 ◽

2005 ◽

Author(s):

C.C. Ko ◽

C.H. Lin ◽

L.P. Li ◽

K.C. Lin ◽

Y.C. Lu ◽

...

Keyword(s):

Low K

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Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. ◽

10.1109/iitc.2005.1499978 ◽

2005 ◽

Cited By ~ 7

Author(s):

R. Sarvari ◽

A. Naeemi ◽

R. Venkatesan ◽

J.D. Meindl

Keyword(s):

Size Effects ◽

Interconnect Networks ◽

And Performance

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Investigation of an advanced SiH/sub 4/ based self-aligned barrier process for Cu BEOL reliability performance improvement on industrial 110 nm technology

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. ◽

10.1109/iitc.2005.1499953 ◽

2005 ◽

Author(s):

P. Dumont-Girard ◽

L.G. Gosset ◽

S. Chhun ◽

M. Juhel ◽

V. Girault ◽

...

Keyword(s):

Performance Improvement ◽

Reliability Performance

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Welcome to IITC 2005

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. ◽

10.1109/iitc.2005.1499888 ◽

2005 ◽

Author(s):

D. Boning ◽

S. Ogawa ◽

D. Gravesteijn

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Effect of ash process on leakage mechanism of Cu/ELK (k=2.5) interconnect for 65/45 nm generation

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. ◽

10.1109/iitc.2005.1499937 ◽

2005 ◽

Cited By ~ 5

Author(s):

J.S. Tsai ◽

Y.N. Su ◽

J.W. Hsu ◽

J.L. Yang ◽

J.H. Shieh ◽

...

Keyword(s):

Leakage Mechanism

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Impact of Cu barrier dielectrics upon stress-induced voiding of dual-damascene copper interconnects

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. ◽

10.1109/iitc.2005.1499916 ◽

2005 ◽

Cited By ~ 1

Author(s):

K. Ishikawa ◽

H. Shimazu ◽

T. Oshima ◽

J. Noguchi ◽

T. Tamaru ◽

...

Keyword(s):

Copper Interconnects ◽

Dual Damascene

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The enabling solution of Cu/low-k planarization technology

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. ◽

10.1109/iitc.2005.1499951 ◽

2005 ◽

Author(s):

Y. Wada ◽

I. Noji ◽

I. Kobata ◽

T. Kohama ◽

A. Fukunaga ◽

...

Keyword(s):

Low K

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Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Wafer-level microfluidic cooling interconnects for GSI

Low resistive and highly reliable Cu dual-damascene interconnect technology using self-formed MnSi/sub x/O/sub y/ barrier layer

Copper-filled through wafer vias with very low inductance

Using a low-k material with k=2.5 formed by a novel quasi-porogen approach for 65 nm Cu/LK interconnects

Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks

Investigation of an advanced SiH/sub 4/ based self-aligned barrier process for Cu BEOL reliability performance improvement on industrial 110 nm technology

Welcome to IITC 2005

Effect of ash process on leakage mechanism of Cu/ELK (k=2.5) interconnect for 65/45 nm generation

Impact of Cu barrier dielectrics upon stress-induced voiding of dual-damascene copper interconnects

The enabling solution of Cu/low-k planarization technology

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.
Latest Publications