Characterization of Trap States at Silicon-On-Insulator (SOI)/Buried Oxide (BOX) Interface by Back Gate Transconductance Characteristics in SOI MOSFETs

2003 ◽  
Vol 42 (Part 1, No. 4B) ◽  
pp. 2004-2008 ◽  
Author(s):  
Yoshikata Nakajima ◽  
Hideki Tomita ◽  
Kenichi Aoto ◽  
Nobuhiro Ito ◽  
Tatsuro Hanajiri ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Trap States ◽  
Back Gate ◽  
Buried Oxide

Fabrication and Electrical Characterization of Ultra-Thin Body and BOX (UTBB) Back Enhanced SOI (BESOI) pMOSFET

2020 ◽  
Vol 15 (1) ◽  
pp. 1-6
Author(s):  
Ricardo Cardoso Rangel ◽  
Katia R. A. Sasaki ◽  
Leonardo Shimizu Yojo ◽  
João Antonio Martino
Keyword(s):  
First Generation ◽  
Electrical Characterization ◽  
Current Drive ◽  
The Body ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Thin Body ◽  
Back Gate ◽  
Buried Oxide ◽  
Complementary Mos Technology

This work analyzes the third generation BESOI MOSFET (Back-Enhanced Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-transistor) built on UTBB (Ultra-Thin Body and Buried Oxide), comparing it to the BESOI with thick buried oxide (first generation). The stronger coupling between front and back interfaces of the UTBB BESOI device improves in 67% the current drive, 122% the maximum transconductance and 223% the body factor. Operating with seven times lower back gate bias, the UTBB BESOI MOSFET presented more compatibility with standard SOI CMOS (Complementary MOS) technology than the BESOI with thick buried oxide.

Towards High-Voltage MOSFETs in Ultrathin FDSOI

2016 ◽  
Vol 25 (01n02) ◽  
pp. 1640005 ◽  
Author(s):  
Antoine Litty ◽  
Sylvie Ortolland ◽  
Dominique Golanski ◽  
Christian Dutto ◽  
Alexandres Dartigues ◽  
...  
Keyword(s):  
High Voltage ◽  
Low Voltage ◽  
Ground Plane ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Drift Region ◽  
Back Gate ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Core Technology

High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.

scholarly journals X-ray characterization of BUSARD chip: A HV-SOI monolithic particle detector with pixel sensors under the buried oxide

2021 ◽  
Vol 16 (12) ◽  
pp. P12030
Author(s):  
F. Alcalde Bessia ◽  
J. Lipovetzky ◽  
I. Perić
Keyword(s):  
Integrated Circuit ◽  
Pulse Height ◽  
Digital Processing ◽  
Silicon On Insulator ◽  
Energy Calibration ◽  
X Ray ◽  
Buried Oxide ◽  
Pixel Sensors ◽  
A Charge

Abstract This work presents the design of BUSARD, an application specific integrated circuit (ASIC) for the detection of ionizing particles. The ASIC is a monolithic active pixel sensor which has been fabricated in a High-Voltage Silicon-On-Insulator (HV-SOI) process that allows the fabrication of a buried N+ diffusion below the Buried OXide (BOX) as a standard processing step. The first version of the chip, BUSARD-A, takes advantage of this buried diffusion as an ionizing particle sensor. It includes a small array of 13×13 pixels, with a pitch of 80 μm, and each pixel has one buried diffusion with a charge amplifier, discriminator with offset tuning and digital processing. The detector has several operation modes including particle counting and Time-over-Threshold (ToT). An initial X-ray characterization of the detector was carried out, obtaining several pulse height and ToT spectra, which then were used to perform the energy calibration of the device. The Molybdenum 𝐊α emission was measured with a standard deviation of 127 e- of ENC by using the analog pulse output, and with 276 e- of ENC by using the ToT digital output. The resolution in ToT mode is dominated by the pixel-to-pixel variation.

Microstructural Characterization of High Dose Oxygen Implanted Silicon

1986 ◽  
Vol 74 ◽  
Author(s):  
J. L. Batstone ◽  
Alice E. White ◽  
K. T. Short ◽  
J. M. Gibson ◽  
D. C. Jacobson
Keyword(s):  
Microstructural Characterization ◽  
Amorphous Structure ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Resolution Imaging ◽  
Buried Oxide ◽  
Transmission Electron ◽  
Resolution Imaging ◽  
Silicon On Insulator Technology

AbstractThe microstructure of oxygen implanted silicon for use in silicon-on- insulator technology has been examined by transmission electron microscopy. A variety of buried oxide layers prepared using oxygen doses below and above that required for stoichiometric SiO2 formation have been studied. High resolution imaging in crosssection has revealed exceptionally flat Si-SiO2 interfaces, comparable to the best thermally grown Si-SiO2 interfaces. Examination of as-implanted material shows a complex interwoven crystalline/amorphous structure which evolves during high temperature (1350–1400° C) annealing into a buried oxide layer.

Characterization of Distribution of Trap States in Silicon-on-Insulator Layers by Front-Gate Characteristics in n-Channel SOI MOSFETs

2008 ◽  
Vol 55 (7) ◽  
pp. 1702-1707 ◽  
Author(s):  
Kenji Kajiwara ◽  
Yoshikata Nakajima ◽  
Tatsuro Hanajiri ◽  
Toru Toyabe ◽  
Takuo Sugano
Keyword(s):  
Silicon On Insulator ◽  
Trap States ◽  
Insulator Layers ◽  
Characterization Of Distribution

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

STUDY OF ELECTRICAL CHARACTERISTIC FOR 50NM AND 10NM SOI BODY THICKNESS IN MOSFET DEVICE

2015 ◽  
Vol 77 (21) ◽  
Author(s):  
M.N.I.A Aziz ◽  
F. Salehuddin ◽  
A.S.M. Zain ◽  
K.E. Kaharudin
Keyword(s):  
Thin Film ◽  
Electrical Characteristic ◽  
Silicon On Insulator ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Doping Density ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Soi Technology ◽  
Better Than

Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.

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