STUDY OF ELECTRICAL CHARACTERISTIC FOR 50NM AND 10NM SOI BODY THICKNESS IN MOSFET DEVICE

2015 ◽  
Vol 77 (21) ◽  
Author(s):  
M.N.I.A Aziz ◽  
F. Salehuddin ◽  
A.S.M. Zain ◽  
K.E. Kaharudin
Keyword(s):  
Thin Film ◽  
Electrical Characteristic ◽  
Silicon On Insulator ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Doping Density ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Soi Technology ◽  
Better Than

Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Reliability challenge of ESD protection: From planner SOI MOSFET to SOI FinFET

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740004 ◽  
Author(s):  
Yibo Jiang ◽  
Hui Bi ◽  
Liangwei Dong ◽  
Qinglong Li
Keyword(s):  
Electrostatic Discharge ◽  
Silicon On Insulator ◽  
Heat Conductor ◽  
Soi Mosfet ◽  
Novel Device ◽  
Thermal Distribution ◽  
Floating Base ◽  
Esd Protection ◽  
Tcad Simulation ◽  
Soi Technology

Implementation of Electrostatic Discharge (ESD) protection in Silicon on Insulator (SOI) technology is a challenge because of the inherent properties of poor heat conductor and heat trapping. In this paper, a novel device as ESD clamp is proposed as Fix-Base SOI FinFET clamp which addresses the troublesome problem of floating base. Moreover, its manufacturing process is compatible to the normal SOI process flow well. Finally, a detailed discussion including current density and thermal distribution are presented with the technique of 3D TCAD simulation.

Evolution of SOI MOSFETs: from Single Gate to Multiple Gates

2003 ◽  
Vol 765 ◽  
Author(s):  
Jean-Pierre Colinge
Keyword(s):  
Current Drive ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Channel Characteristics ◽  
Device Structures ◽  
History Of ◽  
Soi Technology

AbstractTo improve short-channel characteristics and increase current drive, SOI technology is shifting focus from “classical” single-gate MOSFET architectures to multiple-gate device structures. This paper traces the history of single- and multiple-gate SOI MOSFETs and summarizes the electrical characteristics of such devices.

Effects of buried oxide stress on thin-film silicon-on-insulator metal–oxide–semiconductor field-effect transistor

1998 ◽  
Vol 72 (6) ◽  
pp. 677-679 ◽  
Author(s):  
Jong-Wook Lee ◽  
Myung-Hee Nam ◽  
Jeong-Hee Oh ◽  
Ji-Woon Yang ◽  
Won-Chang Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Buried Oxide ◽  
Oxide Stress ◽  
Effect Transistor

Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance

2011 ◽  
Vol 110-116 ◽  
pp. 5150-5154
Author(s):  
K. Senthil Kumar ◽  
Saptarsi Ghosh ◽  
Anup Sarkar ◽  
S. Bhattacharya ◽  
Subir Kumar Sarkar
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Cmos Technology ◽  
Current Drive ◽  
Silicon On Insulator ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Silicon Bulk ◽  
Channel Effects

With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.

scholarly journals Gate Oxide Thickness Influence on the Gate Induced Floating Body Effect in SOI Technology

2008 ◽  
Vol 3 (2) ◽  
pp. 91-95
Author(s):  
Paula G. D. Agopian ◽  
João Antonio Martino ◽  
Eddy Simoen ◽  
Cor Claeys
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Silicon On Insulator ◽  
Floating Body ◽  
Electrical Measurements ◽  
Body Effect ◽  
Soi Mosfet ◽  
Floating Body Effect ◽  
Gate Oxide Thickness ◽  
Soi Technology

In this work, we explore the gate oxide thickness influence on the Gate Induced Floating Body effect (GIFBE). This study was performed through two-dimensional numerical simulations and electrical measurements. The available devices are from 130nm and 65nm Silicon-On-Insulator (SOI) MOSFET technologies. The GIFBE and threshold voltage are evaluated as function of the gate oxide thickness reduction and an overlap tendency of the first and the second transconductance peaks is observed.

scholarly journals Π-Shape Silicon Window for Controlling OFF-Current in Junctionless SOI MOSFET

2021 ◽  
Author(s):  
Mahsa Mehrad ◽  
Meysam Zareiee
Keyword(s):  
The Body ◽  
Maximum Temperature ◽  
The Novel ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Novel Structure ◽  
Channel Effects ◽  
Channel Region

Abstract in this paper a modified junctionless transistor is proposed. The aim of the novel structure is controlling off-current using π-shape silicon window in the buried oxide under the source and the channel regions. The π-shape window changes the potential profile in the channel region in which the conduction band energy get away from the body Fermi energy and rebuild an electrostatic potential. Beside the significant reduced off-current, on current has acceptable value in the novel Silicon Region Junctionless MOSFET (SR-JMOSFET) than Conventional Junctionless MOSFET (C-JMOSFET). Moreover, replacing silicon material instead of silicon dioxide in the buried oxide causes reduced maximum temperature in the channel region. In this situation the heat could transfer to the π-shape silicon window and the temperature reduces in the active region, significantly.The simulation with the two-dimensional ATLAS simulator shows that short channel effects such as subthreshold and DIBL are controlled effectively in the SR-JMOSFET. Also, the optimum values of length and thickness of the π-shape window are defined to obtain the best behavior of the device.

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