In-depth profiling of electron trap states in silicon-on-insulator layers and local mechanical stress near the silicon-on-insulator/buried oxide interface in separation-by-implanted-oxygen wafers

2010 ◽  
Vol 108 (12) ◽  
pp. 124505 ◽  
Author(s):  
Yoshikata Nakajima ◽  
Takahiro Toda ◽  
Tatsuro Hanajiri ◽  
Toru Toyabe ◽  
Takuo Sugano
Keyword(s):  
Mechanical Stress ◽  
Depth Profiling ◽  
Electron Trap ◽  
Silicon On Insulator ◽  
Trap States ◽  
Oxide Interface ◽  
Buried Oxide ◽  
Insulator Layers

Characterization of Trap States at Silicon-On-Insulator (SOI)/Buried Oxide (BOX) Interface by Back Gate Transconductance Characteristics in SOI MOSFETs

2003 ◽  
Vol 42 (Part 1, No. 4B) ◽  
pp. 2004-2008 ◽  
Author(s):  
Yoshikata Nakajima ◽  
Hideki Tomita ◽  
Kenichi Aoto ◽  
Nobuhiro Ito ◽  
Tatsuro Hanajiri ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Trap States ◽  
Back Gate ◽  
Buried Oxide

Characterization of Distribution of Trap States in Silicon-on-Insulator Layers by Front-Gate Characteristics in n-Channel SOI MOSFETs

2008 ◽  
Vol 55 (7) ◽  
pp. 1702-1707 ◽  
Author(s):  
Kenji Kajiwara ◽  
Yoshikata Nakajima ◽  
Tatsuro Hanajiri ◽  
Toru Toyabe ◽  
Takuo Sugano
Keyword(s):  
Silicon On Insulator ◽  
Trap States ◽  
Insulator Layers ◽  
Characterization Of Distribution

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

STUDY OF ELECTRICAL CHARACTERISTIC FOR 50NM AND 10NM SOI BODY THICKNESS IN MOSFET DEVICE

2015 ◽  
Vol 77 (21) ◽  
Author(s):  
M.N.I.A Aziz ◽  
F. Salehuddin ◽  
A.S.M. Zain ◽  
K.E. Kaharudin
Keyword(s):  
Thin Film ◽  
Electrical Characteristic ◽  
Silicon On Insulator ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Doping Density ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Soi Technology ◽  
Better Than

Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.

Effect of Annealing on the Structure of Buried SiO2 Layers Formed By Elevated Temperature High Dose Oxygen Implantation

1985 ◽  
Vol 53 ◽  
Author(s):  
S.J. Krause ◽  
C.O. Jung ◽  
S.R. Wilson ◽  
R.P. Lorigan ◽  
M.E. Burnham
Keyword(s):  
Single Crystal ◽  
Oxide Layer ◽  
Elevated Temperatures ◽  
Superficial Layer ◽  
Silicon On Insulator ◽  
High Dose ◽  
Threading Dislocations ◽  
Heater Temperature ◽  
Buried Oxide ◽  
Structural Differences

ABSTRACTOxygen has been implanted into Si wafers at high doses and elevated temperatures to form a buried SiO2 layer for use in silicon-on-insulator (SOI) structures. Substrate heater temperatures have been varied (300, 400, 450 and 500°C) to determine the effect on the structure of the superficial Si layer through a processing cycle of implantation, annealing, and epitaxial growth. Transmission electron microscopy was used to characterize the structure of the superficial layer. The structure of the samples was examined after implantation, after annealing at 1150°C for 3 hours, and after growth of the epitaxial Si layer. There was a marked effect on the structure of the superficial Si layer due to varying substrate heater temperature during implantation. The single crystal structure of the superficial Si layer was preserved at all implantation temperatures from 300 to 500°C. At the highest heater temperature the superficial Si layer contained larger precipitates and fewer defects than did wafers implanted at lower temperatures. Annealing of the as-implanted wafers significantly reduced structural differences. All wafers had a region of large, amorphous 10 to 50 nm precipitates in the lower two-thirds of the superficial Si layer while in the upper third of the layer there were a few threading dislocations. In wafers implanted at lower temperatures the buried oxide grew at the top surface only. During epitaxial Si growth the buried oxide layer thinned and the precipitate region above and below the oxide layer thickened for all wafers. There were no significant structural differences of the epitaxial Si layer for wafers with different implantation temperatures. The epitaxial layer was high quality single crystal Si and contained a few threading dislocations. Overall, structural differences in the epitaxial Si layer due to differences in implantation temperature were minimal.

Erbium-Silicided Source/Drain Junction Formation by Rapid Thermal Annealing Technique for Decananometer-Scale Schottky Barrier Metal-Oxide-Semiconductor Field- Effect Transistors

2004 ◽  
Vol 810 ◽  
Author(s):  
Moongyu Jang ◽  
Yarkyeon Kim ◽  
Jaeheon Shin ◽  
Kyoungwan Park ◽  
Seongjae Lee
Keyword(s):  
Schottky Barrier ◽  
Annealing Temperature ◽  
Field Effect Transistors ◽  
Growth Conditions ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Oxide Interface ◽  
Silicide Growth ◽  
Stable Growth ◽  
Optimum Annealing Temperature

ABSTRACTThe stable growth conditions of erbium-silicide on silicon-on-insulator (SOI) are investigated considering annealing temperature, SOI and sputtered erbium thickness. From the sheet resistance measurement, X-ray diffraction and Auger electron spectroscopy analysis, the optimum annealing temperature is determined as 500°C. Also, for the stable growth of erbium- silicide on SOI, the sputtered erbium thickness should be less than 1.5 times of SOI thickness. As the SOI thickness decreases below this critical thickness, erbium-rich region is formed at the erbium-silicide and buried-oxide interface. By applying the optimized erbium-silicide growth conditions, 50-nm-gate-length n-type SB-MOSFET is manufactured, which shows the possible usage of erbium-silicide as the source and drain material in the n-type Schottky barrier MOSFETs for decananometer regime applications.

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