Fabrication and Electrical Characterization of Ultra-Thin Body and BOX (UTBB) Back Enhanced SOI (BESOI) pMOSFET

This work analyzes the third generation BESOI MOSFET (Back-Enhanced Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-transistor) built on UTBB (Ultra-Thin Body and Buried Oxide), comparing it to the BESOI with thick buried oxide (first generation). The stronger coupling between front and back interfaces of the UTBB BESOI device improves in 67% the current drive, 122% the maximum transconductance and 223% the body factor. Operating with seven times lower back gate bias, the UTBB BESOI MOSFET presented more compatibility with standard SOI CMOS (Complementary MOS) technology than the BESOI with thick buried oxide.

A Multilayer High-Speed Magnetic-Tunnel-Junction Magneto-resistive RAM Structure with Read-Disturb-Detection Circuit by Using Nano-Electronics Quantum Dot Cellular Method

In this nano technical world the “Complementary MOS technology” can be replaced by using “Quantum Dot Cellular Automata” with reversible logical phenomenon to achieve a fault tolerant, low-cost nano electronics formation by feature size, latency and power consumption minimization. The memory is one of the most interesting part of research in this digital world. This paper represents an optimizing highfrequency (in THz) reversible design of a “Random Access Memory” which is simulated by using nano electronics ‘QCA’ simulator to get a better performance than “Complementary MOS technology” with high frequency (in THz), less occupied area and dissipated power. This paper also shows a highlyflexible magnetic quantum cell logic-design and MTJ logical representation which is used for non-volatile MRAM which is widely used in digital electronics world and as a part of aerospace and military device. A reversible nano electronics formation of the control logic to select the word-line and inputline of the MRAM also presented here. The reversible-logic can avoid the information-loss in memory device by zero-heating technique. Non-reversible formations dissipate ‘KTln2’ energy per bit which can be ignored in reversible formation. But, read disturb at low write current is a major issue of MTJ MRAM due to the same path of read/write current path. In this paper a three dimension reversible “Read Disturb Detection Circuit” is formed by nano electronics ‘QCA’ technology which bit-wise follows the control logic of read-disturb-detection technique and the same figure also simulated by ‘VHDL’ coding in Xilinx software to prove the advantages of ‘QCA’ technology contrast to Xilinx This paper also focuses on the correspondence between change of temperature and supply power.

InGaAs Metal Oxide Semiconductor Devices with Ga2O3(Gd2O3) High-κ Dielectrics for Science and Technology beyond Si CMOS

An overview is given on scientific and device advances for InGaAs metal oxide semiconductor heterostructures and inversion channel metal oxide semiconductor field-effect transistors (MOSFETs), with emphasis on results using ultrahigh vacuum-deposited Ga2O3(Gd2O3) [GGO] as high-κ dielectrics. Regardless of the approaches used to deposit high-κ dielectrics on InGaAs, critical material and electrical parameters of fabricating inversion channel InGaAs MOSFETs must be ready for complementary MOS technology beyond the 16-nm node, and some of these parameters have been achieved. These parameters include low interfacial density of states; low electrical leakage currents; high-temperature (800–900°C) thermal stability for high-κ dielectrics/InGaAs heterostructures, where the amorphous oxide structure and atomically smooth and sharp interfaces are retained; and oxide scalability with a capacitance equivalent thickness of ≤1 nm. Interfacial chemical properties and band parameters, which are important for device design in the high κs/InGaAs, have been thoroughly studied. Representative enhancement-mode InGaAs MOSFETs are compared and correlated with the interfacial structures. Deposition methods and electrical characteristics of high-κ dielectrics on InGaA are discussed. The inversion channel InGaAs MOSFETs of 0.4–1.0 μm gate length have exhibited excellent device performance in terms of drain current and transconductance.