General Modeling Method of Threshold-Type Multivalued Memristor and Its Application in Digital Logic Circuits

This paper presents a general modeling method for threshold-type multivalued memristors. Through this memristor modeling method, it is very simple to establish threshold-type memristor behavior models with different numbers of memristance elements, and these models are verified by numerical MATLAB simulations. A corresponding circuit-level SPICE model of the ternary memristor behavior model is developed and simulated in LTspice, shown to be consistent with the MATLAB results. Finally, the SPICE model is used to design the AND gate, OR gate, and three NOT gates of ternary state-based logic, and the effectiveness of the circuit is proved by LTSpice simulation.

An FPGA Based Hardware Accelerator for Remote Surveillance Cameras

<p>The Blackeye II camera, produced by Kinopta, is used for remote security, conservation and traffic flow surveillance. The camera uses an image sensor to acquire photographs which undergo image processing and JPEG encoding on a microprocessor. Although the microprocessor performs other tasks, it is the processing and encoding of images that limit the frame rate of the camera to 2 frames per second (fps). Clients have requested an increase to 12.5 fps while adding more image processing to each photograph. The current microprocessor-based system is unable to achieve this. Custom digital logic systems perform well on processes that naturally form a pipeline, such as the Blackeye II image processing system. This project develops a digital logic system based on an FPGA to receive images from the image sensor, perform the required image processing operations, encode the images in JPEG format and send them on to the microprocessor. The objective is to implement a proof of concept device based upon the Blackeye II’s existing hardware and an FPGA development board. It will implement the proposed pipeline including one example of an image processing operation. A JPEG encoder is designed to process the 752 × 480 greyscale photographs from the image processor in real time. The JPEG encoder consists of four stages: discrete cosine transform (DCT), quantisation, zig-zag buffer and Huffman encoder. The DCT design is based upon the work of Woods et al. [1], which is improved on. An analysis of the relationship between precision and accuracy in the DCT and quantisation stages is used to minimise the system’s resource requirements. The JPEG encoder is successfully tested in simulation. Input and output stages are added to the design. The input stage receives data from the image sensor and removes breaks in the data stream. The output stage must concatenate the data from the JPEG encoder and transmit it to the microprocessor via the microprocessor’s ISI (image sensor interface) peripheral. An image sharpening filter is developed and inserted into the pipeline between the input and JPEG encoder. Because remote surveillance cameras are battery powered, the minimisation of power consumption is a key concern. To minimise power consumption a mechanism is introduced to track those modules in the pipeline that are in use at any time. Any not in use are paused by gating the module’s clock source. Once the system is complete and tested in simulation it is loaded into hardware. The FPGA development board is attached to the image sensor board and microprocessor board of the Blackeye II camera by a purpose-built breakout board. Plugging the microprocessor board into a PC provides a live stream of images proving the successful operation of the FPGA system. The project objectives were exceeded by increasing the frame rate of the Blackeye II to 20 fps, which will not decrease with additional image processing operations. The project was viewed as a success by Kinopta, who have committed to its further development.</p>

An FPGA Based Hardware Accelerator for Remote Surveillance Cameras

<p>The Blackeye II camera, produced by Kinopta, is used for remote security, conservation and traffic flow surveillance. The camera uses an image sensor to acquire photographs which undergo image processing and JPEG encoding on a microprocessor. Although the microprocessor performs other tasks, it is the processing and encoding of images that limit the frame rate of the camera to 2 frames per second (fps). Clients have requested an increase to 12.5 fps while adding more image processing to each photograph. The current microprocessor-based system is unable to achieve this. Custom digital logic systems perform well on processes that naturally form a pipeline, such as the Blackeye II image processing system. This project develops a digital logic system based on an FPGA to receive images from the image sensor, perform the required image processing operations, encode the images in JPEG format and send them on to the microprocessor. The objective is to implement a proof of concept device based upon the Blackeye II’s existing hardware and an FPGA development board. It will implement the proposed pipeline including one example of an image processing operation. A JPEG encoder is designed to process the 752 × 480 greyscale photographs from the image processor in real time. The JPEG encoder consists of four stages: discrete cosine transform (DCT), quantisation, zig-zag buffer and Huffman encoder. The DCT design is based upon the work of Woods et al. [1], which is improved on. An analysis of the relationship between precision and accuracy in the DCT and quantisation stages is used to minimise the system’s resource requirements. The JPEG encoder is successfully tested in simulation. Input and output stages are added to the design. The input stage receives data from the image sensor and removes breaks in the data stream. The output stage must concatenate the data from the JPEG encoder and transmit it to the microprocessor via the microprocessor’s ISI (image sensor interface) peripheral. An image sharpening filter is developed and inserted into the pipeline between the input and JPEG encoder. Because remote surveillance cameras are battery powered, the minimisation of power consumption is a key concern. To minimise power consumption a mechanism is introduced to track those modules in the pipeline that are in use at any time. Any not in use are paused by gating the module’s clock source. Once the system is complete and tested in simulation it is loaded into hardware. The FPGA development board is attached to the image sensor board and microprocessor board of the Blackeye II camera by a purpose-built breakout board. Plugging the microprocessor board into a PC provides a live stream of images proving the successful operation of the FPGA system. The project objectives were exceeded by increasing the frame rate of the Blackeye II to 20 fps, which will not decrease with additional image processing operations. The project was viewed as a success by Kinopta, who have committed to its further development.</p>

Detection of Unwanted Odors using Unmasking Odor Algorithm (UOA)

A new approach to detection of the existence of unwanted odors after spraying the smart home and vehicular environment with perfumes is considered in the work. The approach is based on registering the response curve of an array of sensors to perfumes and to odors such as herbs, then using the proposed intersection algorithm to uncover the ability of the perfume to mask specific odors. Three odors (herbs) and three perfumes are tried and resulted in the ability of perfumes to mask two of the herbs, one deeper than the other. The response curve intersection technique (RCIT) provides the ability to unmask unwanted odor existence, thus forms the heart of the unmasking odor algorithms (UOA). Mathematical equations are used to prove the concept with digital logic is further used to support the presented algorithm. The research found that using the proposed technique, an odor masked by spraying of perfumes can be unmasked using the RCIT as the case in herb 3 presented in the work. The work also showed the unique curve shape for both perfumes and herbs and the fact that some herbs can be easily masked and hidden within the response of perfumes. In addition, it is shown that the perfumes response is much more complex compared to herbs

Seven-Level Symmetrical Series/Parallel Multilevel Inverter with PWM Technique Using Digital Logic

This paper attempts to come up with a proposed configuration of Multilevel inverters with a lesser number of switches that are smaller in size, lesser in cost and with a higher efficiency. Designing an inverter topology with a lesser number of switches and proper control technique is the major challenge. cascaded H-Bridge (CHB) topology are more popular among the existing configurations of multilevel inverters (MLI). Even though it can produce more levels, it needs to accommodate a huge number of switches for higher levels. The focus of this paper is to reduce the number of components for the same voltage level of cascaded H- Bridge configuration. In addition to that, generating the gating pulses for the switches is difficult when there is an asymmetry in the switches. A new symmetrical series/parallel configuration is proposed with reduced switch count and the pulse width modulation (PWM) technique is implemented with digital logic to generate the required gating pulses for the switches. The total harmonic distortion (THDI) of the output current is reduced with this PWM technique. The simulation has been carried out in MATLAB/Simulink software for both R (resistive) and R-L (resistive -inductive) loads.