compensation voltage
Recently Published Documents


TOTAL DOCUMENTS

24
(FIVE YEARS 2)

H-INDEX

7
(FIVE YEARS 0)

2021 ◽  
Vol 2108 (1) ◽  
pp. 012081
Author(s):  
Xinwei Cao(Cao) ◽  
Youjun Zhang(Zhang) ◽  
Zhengzheng Sun(Sun)

Abstract Aiming at the defects of DC energy storage elements, complex structure and large volume of unified power flow controller (UPFC), the paper combines flying capacitor multilevel technology and voltage vector synthesis technology with unified direct power flow controller. A three-level direct power flow controller (3L-DPFC) and a new control strategy are proposed. By obtaining the power parameters of the receiving end and substituting them into the derived calculation formula, the compensation voltage can be deduced to adjust the phase and amplitude, and the change relationship between the compensation voltage and the power parameters of the receiving end can be calculated through multiple groups of data, so as to adjust the active power flow and reactive power flow in the power grid. Compared with the unified direct power flow controller, it has the advantages of no DC energy storage element, small volume, simple structure, and the voltage stress of each switch is reduced by half, which reduces the failure rate and economic cost of the controller. In the paper, the topology and control strategy of three-level synthetic DPFC are described in detail, and its buck AC conversion theoretical analysis is verified by simulation.


Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 92 ◽  
Author(s):  
Jeong-Woo Lim ◽  
Hanyoung Bu ◽  
Younghoon Cho

This paper proposes a novel three-phase voltage source inverter dead-time compensation strategy for accurate compensation in wide current regions of the inverter. In particular, an analysis of the output voltage distortion of the inverter, which appears as parasitic components of the switches, was conducted for proper voltage compensation in the low current region, and an on-line compensation voltage controller was proposed. Additionally, a new trapezoidal compensation voltage implementation method using the current phase was proposed to simplify realizing the trapezoidal shape of the three-phase compensation voltages. Finally, when the proposed dead-time compensation strategy was applied, the maximum phase voltage magnitude in the linear modulation voltage regions was defined to achieve smooth operation even at high modulation index. Simulations and experiments were conducted to verify the performance of the proposed dead-time compensation scheme.


Author(s):  
Jeong-Woo Lim ◽  
Hanyoung Bu ◽  
Younghoon Cho

This paper proposes a novel three-phase voltage source inverter dead-time compensation strategy for accurate compensation in wide current regions of the inverter. In particular, an analysis of the output voltage distortion of the inverter, which appears as parasitic components of the switches, has been conducted for proper voltage compensation in the low current region, and an on-line compensation voltage controller has been proposed. Also, a new trapezoidal compensation voltage implementation method using the current phase is proposed to simplify realizing the trapezoidal shape of the three-phase compensation voltages. Finally, when the proposed dead-time compensation strategy is applied, the maximum phase voltage magnitude in the linear modulation voltage regions is defined to achieve smooth operation even at high modulation index. Simulations and experiments were conducted to verify the performance of the proposed dead-time compensation scheme.


2016 ◽  
Vol 26 (03) ◽  
pp. 1750047
Author(s):  
Yiqiang Zhao ◽  
Jingshuai Wang ◽  
Yun Sheng

This paper proposes a mixed signal DC offset cancellation (DCOC) which does not cause the near-DC rejection for zero-IF receiver. To achieve low output offset efficiently, the DCOC consisting of a comparator, a digital logic controller and compensation voltage generators is used. It utilizes current sources arrays that are controlled by thermometer code to generate the compensation voltage. The proposed DCOC is implemented in GF 0.18 [Formula: see text]m CMOS process. The measurement results show that the proposed calibration method can reduce the offset residue to less than 80 mV and the total calibration time is less than 13 [Formula: see text]s. It only drains 60 [Formula: see text]A from a 3.3 V supply.


Sign in / Sign up

Export Citation Format

Share Document