Next Gen Test-Vehicle to Simulate Thermal Load for IoT FPGA Applications

2018 ◽  
Author(s):  
Suresh Parameswaran ◽  
Gamal Refai-Ahmed ◽  
Suresh Ramalingam ◽  
Boon Ang
Keyword(s):  
Power Dissipation ◽  
Evaluation System ◽  
Flip Chip ◽  
Semiconductor Device ◽  
Thermal Interface Material ◽  
Feature Size ◽  
Test Vehicle ◽  
Circuit Performance ◽  
Development Cycle ◽  
Size Scales

As semiconductor device feature size scales and circuit performance increases, power dissipation and thermal management are becoming very important. Attention to thermal considerations is required throughout the chip development cycle from preliminary architecture planning to deployment on customer board and beyond. This paper describes a versatile thermal test vehicle that can be used to address these requirements. We discuss the architecture and implementation of a specially designed test-vehicle chip, followed by its operation. The programmability and flexibility of this vehicle will be highlighted. In addition, we cover other usage of this vehicle which includes modelling of chip-level thermal behavior with different floorplan, simulating thermal loads in IoT FPGA applications, cross-calibrating thermal numerical simulators with measured silicon data and evaluating the thermal impact of different package form-factor / material (such as thermal interface material) and cooling solutions. The abovementioned chip was fabricated using 0.18um technology and assembled in a flip-chip package. The reminder of this evaluation system is a simple, inexpensive tester from which a software is run to program the chip and to measure the spatial & temporal temperature values. Measured thermal data from different use cases are presented in this paper.

Removing W Polymer Residue from BEOL Structures Using DSP+ (Dilute Sulfuric-Peroxide-HF) Mixture – A Case Study

2012 ◽  
Vol 195 ◽  
pp. 128-131 ◽  
Author(s):  
Hun Hee Lee ◽  
Min Sang Yun ◽  
Hyun Wook Lee ◽  
Jin Goo Park
Keyword(s):  
High Speed ◽  
Semiconductor Device ◽  
Environmental Issues ◽  
Low Power Consumption ◽  
Device Performance ◽  
Metal Gate ◽  
Feature Size ◽  
High K ◽  
Removal Of Metal

As the feature size of semiconductor device shrinks continuously, various high-K metals for 3-D structures have been applied to improve the device performance, such as high speed and low power consumption. Metal gate fabrication requires the removal of metal and polymer residues after etching process without causing any undesired etching and corrosion of metals. The conventional sulfuric-peroxide mixture (SPM) has many disadvantages like the corrosion of metals, environmental issues etc., DSP+(dilute sulfuric-peroxide-HF mixture) chemical is currently used for the removal of post etch residues on device surface, to replace the conventional SPM cleaning [. Due to the increased usage of metal gate in devices in recent times, the application of DSP+chemicals for cleaning processes also increases [.

Molding Recipe Study for MUF Solder Crack Improvement

2018 ◽  
Vol 2018 (1) ◽  
pp. 000121-000124
Author(s):  
Scott Chen ◽  
Leander Liang ◽  
Pallas Hsu ◽  
Tim Tsai ◽  
Mason Liang ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Flow Simulation ◽  
Test Vehicle ◽  
Chip Technology ◽  
Solder Bumps ◽  
Capillary Underfill ◽  
Mold Flow ◽  
Profile Reduction ◽  
Transfer Pressure

Abstract In recent years, flip chip technology becomes more and more important with benefits of thin package profile, reduction of package outline, and excellent electrical and thermal performance by connection of copper pillar bumps (CuP) or C4 solder bumps. In order to fill the die gap to prevent voids problem, two encapsulated solutions could be applied: capillary underfill (CUF) and molded underfill (MUF). In general comparison, CUF means to dispense underfill first to fill in die gap then proceed over-molding afterward; and MUF is directly fill under and above die by mold compound. The advantages of MUF solution are low cost and high throughput, however, it will suffer other assembly issues such as solder extrusion and solder crack, and might result in potential function failure. To form these kinds of defects, we suspected that solder will plastically deform under thermal stress treatment, which comes from unbalance mold transfer pressure and material expansion stress during thermal process. In this article, we have tried to investigate the mechanism of solder crack through molding recipe DOE (Design of Experiment) and mold flow simulation. The test vehicle is 12 × 12 mm2 FCCSP, with 6 × 5 mm2 die size. The bump type is copper pillar bump and pitch/size are 126 um and 35 × 60 um2, respectively. The molding recipe has been evaluated by cross section, and it revealed that molding transfer time and molding temperature are directions toward improvement of solder crack issue.

Use of Wafer Applied Underfill for 3D Stacking

2011 ◽  
Vol 2011 (1) ◽  
pp. 000008-000016 ◽  
Author(s):  
Antonio La Manna ◽  
K. J. Rebibis ◽  
C. Gerets ◽  
E. Beyne
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Initial Assessment ◽  
Test Vehicle ◽  
Differential Movement ◽  
The Right ◽  
3D Stacking ◽  
Material Uniformity ◽  
Work Done

A key element for improving 3D stacking reliability is the choice of the right Underfill materials. The Underfill is a specialized adhesive that has the main purposes of locking top and bottom dies; it must fill the gap between bumps and between dies, while reducing the differential movement that would occur during thermal cycling. Traditional underfill processes are based on local dispensing after solder bump reflow (Capillary dispensing), or before flip chip operation with no need of reflow (No Flow Underfill, NUF). In case of 3D stacking, such processes present some limitations: need of a dispensing area (die size increase); material flowing (spacing between dies) and cost (low throughput). After an introduction on typical underfill applications like die-to-package and die-die assembly, we report the work done to assess the properties of several Wafer Applied Underfill (WAUF) materials and their integration in 3D stacking. These materials have been initially applied on silicon wafers in order to assess the minimum achievable thickness and the material uniformity. The wafers have been coated by using different methods: spin coating and film lamination. After this initial assessment, the most promising materials have been used for 3D stacking. The test vehicle used has Cu/Sn μbumps with a pitch of 40μm. The quality of the materials is judged by electrical test, SAM (Surface Acoustic Microscope) and X-SEM (Scanning Electron Microscope).

Design and Direct Assembly of 2.5D/3D Rigid Silicon Interposer on PCB

2014 ◽  
Vol 2014 (1) ◽  
pp. 000783-000786 ◽  
Author(s):  
Farhang Yazdani
Keyword(s):  
Flip Chip ◽  
Thermal Stresses ◽  
Stress Test ◽  
Temperature Cycle ◽  
3D Integration ◽  
Test Vehicle ◽  
Direct Assembly ◽  
Solder Balls ◽  
Present Design ◽  
The Cost

Silicon interposer is emerging as a vehicle for integrating dies with sub 50um bump pitch in 2.5D/3D configuration. Benefits of 2.5D/3D integration are well explained in the literature, however, cost and reliability is a major concern especially with the increase in interposer size. Among the challenges, reliability issues such as warpage, cracks and thermal-stresses must be managed, in addition, multi-layer build-up flip chip substrate cost and its impact on the overall yield must be considered. Because of these challenges, 2.5D/3D silicon interposer has developed a reputation as a costly process. To overcome the reliability challenges and cost associated with typical thin interposer manufacturing and assembly, a rigid silicon interposer type structure is disclosed. In this study, interposer with thickness of greater than 300um is referred to as rigid interposer. Rigid silicon interposer is directly assembled on PCB without the need for intermediary substrate. This eliminates the need for an intermediary substrate, thin wafer handling, wafer bonding/debonding procedures and Through Silicon Via (TSV) reveal processes, thus, substantially reducing the cost of 2.5D/3D integrated products while improving reliability. A 10X10mm2 rigid silicon interposer test vehicle with 310um thickness was designed and fabricated. BGA side of the interposer with 1mm ball pitch was bumped with eutectic solder balls through a reflow process. Interposer was then assembled on a 50X50mm2 FR-4 PCB. We present design and direct assembly of the rigid silicon interposer on PCB followed by temperature cycle results using CSAM images at 250, 500, 750 and 1000 cycles. It is shown that all samples successfully passed the temperature cycle stress test.

Thermal Management for Chip-Scale Atomic Clocks

2005 ◽  
Author(s):  
Alexander Laws ◽  
Richard Y. J. Chang ◽  
Victor M. Bright ◽  
Y. C. Lee
Keyword(s):  
Thermal Management ◽  
Power Dissipation ◽  
Waste Heat ◽  
Large Temperature ◽  
Cavity Surface ◽  
Atomic Clocks ◽  
Test Vehicle ◽  
Ambient Temperatures ◽  
Thermal Test ◽  
Vertical Cavity Surface

Power dissipation of chip-scale atomic clocks is one of the major design considerations. The largest power dissipation is for temperature control of the vertical-cavity surface-emitting laser (VCSEL) and cesium vapor cell. For example, the temperature of the VCSEL and Cs cell have to both be at 70±0.1°C or there will be frequency shift which will ruin the lock of the clock. These temperatures have to be maintained even under a large temperature variation such as −40°C to 50°C. There are three major thermal designs to consider: a) micro-heaters to fine-tune the temperatures of VCSEL and Cs cell, b) use of waste heat from other units to heat the system when outside temperature is low, and c) use of a thermal switch to release any extra waste heat when ambient temperatures are high. These three thermal designs have been incorporated in to a thermal test vehicle, which will be used to develop a thermal management design for the clock. This paper describes the proposed clock design, creation of the thermal test vehicle and development of a bimetallic snap based thermal conduction switch. The switch has been demonstrated to change thermal resistance from 52.9±2.8 K/W when the switch is open to 19.5±1.1 K/W with the switch closed.

Flip Chip Thermal Test Vehicle Design: Requirements, Evaluations, and Validations

2003 ◽  
Author(s):  
Teck Joo Goh ◽  
Chia-Pin Chiu ◽  
K. N. Seetharamu ◽  
G. A. Quadir ◽  
Z. A. Zainal
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Thermal Characterization ◽  
Circuit Board ◽  
Vehicle Design ◽  
Test Chip ◽  
Test Vehicle ◽  
Design Processes ◽  
Thermal Test ◽  
Design Requirements

This paper reviews the design of a flip chip thermal test vehicle. Design requirements for different applications such as thermal characterization, assembly process optimization, and product burn-in simulation are outlined. The design processes of different thermal test chip structures including the temperature sensor and passive heaters are described in detail. In addition, the design of fireball heater, a novel test chip structure used for evaluating the effectiveness of heat spreading of advanced thermal solutions, is also illustrated. The design considerations and processes of the package substrate and printed circuit board with special emphasis on the physical routing of the thermal test chip structures are described. These design processes are supported with thermal data from various finite-element analyses (FEA) carried out to evaluate the capability and limitations of thermal test vehicle design. Design optimization as the outcome of these analyses is also elaborated. Lastly, the validation and calibration procedures of the thermal test vehicle are presented in this paper.

Evaluation of Bare Die Chip Reliability Due to Underfill Materials During Mechanical Actuation and Thermal Cycling

2005 ◽  
Author(s):  
Arv Sinha
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Bond Line ◽  
Thermal Interface Material ◽  
High Power Density ◽  
The Finite Element Method ◽  
Chip Design ◽  
Thermal Interface ◽  
Ball Grid Arrays ◽  
Mechanical Actuation

Use of underfill materials to encapsulate ball grid arrays (BGAs) or chip scale packages (CSPs) have become very important in increasing the reliability of area array packages [1]. Underfill enhances the reliability of flip-chip devices by distributing the thermo-mechanical stresses [2, 3]. These stresses are generated due to mechanical actuation and coefficient of thermal expansion mismatch (CTE) [3]. They are required due to high power density of the current chip design to achieve fine bond line at the thermal interface material in order to dissipate heat. In this paper, details of reliability assessment using the finite element method and actual test data will be presented and discussed.

FUNDAMENTALS OF THE SQUEEZE-FLOW BETWEEN A HEAT SINK AND A FLIP-CHIP

2008 ◽  
Vol 32 (3-4) ◽  
pp. 467-486 ◽  
Author(s):  
M.A. Marois ◽  
M. Lacroix
Keyword(s):  
Heat Sink ◽  
Flip Chip ◽  
String Model ◽  
Thermal Interface Material ◽  
Squeeze Flow ◽  
Back Side ◽  
Two Dimensional ◽  
Particle Volume ◽  
Volume Fractions ◽  
Drop Flow

The paper presents the fundamentals of the squeeze-flow of the thermal interface material (TIM) that takes place during the pressing of a heat sink to the back side of a flip-chip is studied. A two-dimensional string model is developed for predicting the time-varying plate separation and squeeze-rate in terms of the squeeze force. The predictions are compared to a one-dimensional string model and to a squeeze-drop flow model. Results indicate that the flow resulting from the squeezing of a string of TIM between two rigid plates is truly two-dimensional. The effect of surface tension and of the heat transfer is found to be negligible under the assembly conditions. The flow behaviour of the TIM with suspensions of high thermal conductivity particles is also investigated. It is shown that the fluid remains Newtonian for particle volume fractions smaller than 30%. For volume fractions larger than 30%, the fluid becomes Non-Newtonian during the early stages of the squeezing process, i.e. for t ≤ 1s. In the later stages however (t > 10s), the fluid may be considered Newtonian.

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