Design and Direct Assembly of 2.5D/3D Rigid Silicon Interposer on PCB

2014 ◽  
Vol 2014 (1) ◽  
pp. 000783-000786 ◽  
Author(s):  
Farhang Yazdani
Keyword(s):  
Flip Chip ◽  
Thermal Stresses ◽  
Stress Test ◽  
Temperature Cycle ◽  
3D Integration ◽  
Test Vehicle ◽  
Direct Assembly ◽  
Solder Balls ◽  
Present Design ◽  
The Cost

Silicon interposer is emerging as a vehicle for integrating dies with sub 50um bump pitch in 2.5D/3D configuration. Benefits of 2.5D/3D integration are well explained in the literature, however, cost and reliability is a major concern especially with the increase in interposer size. Among the challenges, reliability issues such as warpage, cracks and thermal-stresses must be managed, in addition, multi-layer build-up flip chip substrate cost and its impact on the overall yield must be considered. Because of these challenges, 2.5D/3D silicon interposer has developed a reputation as a costly process. To overcome the reliability challenges and cost associated with typical thin interposer manufacturing and assembly, a rigid silicon interposer type structure is disclosed. In this study, interposer with thickness of greater than 300um is referred to as rigid interposer. Rigid silicon interposer is directly assembled on PCB without the need for intermediary substrate. This eliminates the need for an intermediary substrate, thin wafer handling, wafer bonding/debonding procedures and Through Silicon Via (TSV) reveal processes, thus, substantially reducing the cost of 2.5D/3D integrated products while improving reliability. A 10X10mm2 rigid silicon interposer test vehicle with 310um thickness was designed and fabricated. BGA side of the interposer with 1mm ball pitch was bumped with eutectic solder balls through a reflow process. Interposer was then assembled on a 50X50mm2 FR-4 PCB. We present design and direct assembly of the rigid silicon interposer on PCB followed by temperature cycle results using CSAM images at 250, 500, 750 and 1000 cycles. It is shown that all samples successfully passed the temperature cycle stress test.

Pure Chemical Reduction of Tin Oxides to Metallic Tin by Atmospheric Plasma to Improve Interconnection Reflow of Pb-free Solders

2015 ◽  
Vol 2015 (1) ◽  
pp. 000725-000729
Author(s):  
Kang-Wook Lee ◽  
Katsuyuki Sakuma ◽  
Thomas Lombardi ◽  
Jason Rowland ◽  
David Lewison ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Flip Chip ◽  
Chemical Reduction ◽  
Surface Preparation ◽  
Poor Quality ◽  
Atmospheric Plasma ◽  
Tin Alloys ◽  
Tin Oxides ◽  
Solder Balls ◽  
The Cost

Tin alloys are widely used as solder for electronic interconnections. Tin solder surfaces tend to have tin oxides which need to be removed to improve the yield of interconnection reflow processes such as flip chip joining. Conventionally, a strong flux is employed to remove these oxides, however this process has the drawbacks of leaving flux residue which can cause underfill delamination or require a high-cost cleaning process. As solder bump volumes and bump-to-bump spacing decrease, these problems become more difficult to manage in manufacturing. We propose the use of Atmospheric Plasma to reduce these oxides from the bump surfaces to enable the use of very light fluxes, or no flux at all. This process has the advantages of plasma surface preparation without the cost and throughput penalty of vacuum plasma processes. Such a process can increase throughput and yield while reducing the cost. We describe an experiment in which tin foils were treated with a reducing-chemistry Atmospheric Plasma process and then analyzed with X-ray photoelectron spectroscopy (XPS) and Auger Electron Spectroscopy (AES). AES depth profile analyses indicate that the thickness of tin oxides was significantly reduced by the plasma. There was no evidence for any etching of underlying elemental tin. These results suggest that tin oxides are reduced to metallic tin without etching of the underlying tin metal. In another similar experiment using semiconductor chips with SnAg solders, XPS results suggest that the tin oxides were again reduced to metallic tin. In flip chip joining, the joining process with such Atmospheric Plasma-treated chips achieved high interconnect yield, even in the case of poor quality solder balls with excessive oxidation. It is our understanding that the pure chemical reduction of tin oxides with atmospheric plasma in ambient had not been previously reported.

Solder-Joint Reliability of BGA Packages in Automotive Applications

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000236-000257 ◽  
Author(s):  
Burton Carpenter ◽  
Andrew Mawer ◽  
Mollie Benson ◽  
John Arthur ◽  
Betty Young
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Performance Test ◽  
Stress Test ◽  
Circuit Board ◽  
Cycle Performance ◽  
Temperature Cycle ◽  
Automotive Applications ◽  
Bga Packages ◽  
Board Level

The solder-joint interconnect between an IC component and the PCB (printed circuit board) is a critical link in the system overall reliability. Trends in the automotive market are driving increased focus on solder-joint performance: (1) increasing electronics content for new functions, especially for ADAS (advanced driver-assistance systems), (2) use in safety critical systems and sub-systems, (3) decreasing interconnect pitches which reduces the stand-off and available solder, (4) increasing industry reliability expectations, and (5) package variations (ex. multi-die). In particular, BGA (Ball Grid Array) packages are used throughout the vehicle across various systems including engine control, braking, communication, infotainment, and radar to name only a few. Among these, under-the-hood applications often require high sustained operating temperatures and many heating/cooling cycles during the vehicle lifetime. The reliability of these interconnects is routinely assessed by cyclical thermal stress (temperate cycling) of components mounted to boards. While AEC (Automotive Electronics Council) offers no standards for solder-joint testing (for example, board level reliability criteria is not included in the AEC Q100 “Failure Mechanism Based Stress Test Qualification for Integrated Circuits”), IPC 9701A “Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments” can be followed. For automotive under-the-hood the specified cycle range is 40°C to 125°C (TC3). This paper summarizes the BL-TC (board level temperature cycle) performance of various BGA packages used in automotive applications. In all cases the test vehicle packages were daisy-chain versions of production devices, while maintaining critical features such as BGA footprint, physical dimensions, BOM (bill of materials), die size and thickness and substrate layer metal densities. All used Pb-free solders for both the BGA solder ball and the paste printed onto the PCB. The PCB designs were complementary to the packages establishing daisy-chain connections winding through the PCB, the solder-joint and package substrate. Each chain (net) was continuously monitored in situ during cycling. An event detector logged a failure when a net resistance exceeded 300 ohms. Wirebonded and flip chip packages were studied, ranging in size from 10mm to 29mm with BGA pitches including 0.65mm, 0.80mm and 1.00mm. In addition to these primary attributes, various other factors were found to alter the solder-joint lifetimes. For example, increasing BGA pad and solder sphere diameters improved solder-joint lifetime, but increasing the PCB pad diameter often did not. Among solder materials, eutectic SnAg typically showed longer lifetimes than other high Ag SAC alloys such as SAC305 and SAC405. The addition of Bi to the SAC alloy showed promise for further improvements. Other factors that were studied include die thickness, die size, and BGA pad finish. Both mechanical cross-section and dye penetrant analysis (dye-and-pry) were employed for failure analysis, enabling study of crack propagation and crack location within the solder-joint. Additionally, failure location (failing solder-joint) was identified for each as package corner, under the die edge, or package center in a predictable pattern depending on the package type. Examined in total, two opposing trends will force future innovation. Industry reliability requirements continue to drive expectations (i.e. cycles to failure) higher, while increasing package size and decreasing pitch will naturally reduce the solder-joint lifetimes. Solutions will be found in package design, package material and solder selections.

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages (WLCSP)

2011 ◽  
Author(s):  
Pushkraj Tumne ◽  
Vikram Venkatadri ◽  
Santosh Kudtarkar ◽  
Michael Delaus ◽  
Daryl Santos ◽  
...  
Keyword(s):  
Flip Chip ◽  
Bulk Solder ◽  
Consumer Electronics ◽  
Drop Test ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Wafer Level ◽  
Cross Sectional ◽  
Right Censored Data ◽  
Solder Balls

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

scholarly journals FCCSP IMC growth under reliability stress follows automotive criteria

2019 ◽  
Vol 3 (1) ◽  
pp. 70-83
Author(s):  
Wei Wei Liu ◽  
Berdy Weng ◽  
Scott Chen
Keyword(s):  
High Temperature ◽  
Flip Chip ◽  
Stress Test ◽  
Temperature Cycling ◽  
Content Type ◽  
Initial Stage ◽  
High Temperature Storage ◽  
Temperature Cycling Test ◽  
Temperature Storage

Purpose The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu3Sn and Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture. Design/methodology/approach The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology. Findings The Cu6Sn5 intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu3Sn IMC. Cu6Sn5 IMC will convert to Cu3Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu3Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni3Sn4 IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni3Sn4 IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell. Research limitations/implications The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design. Practical implications This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology. Originality/value The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.

scholarly journals Growth Kinetics of Reaction Layers in Flip Chip Joints with Cu-cored Lead-free Solder Balls

2004 ◽  
Vol 45 (3) ◽  
pp. 754-758 ◽  
Author(s):  
Ikuo Shohji ◽  
Yuji Shiratori ◽  
Hiroshi Yoshida ◽  
Masahiko Mizukami ◽  
Akira Ichida
Keyword(s):  
Growth Kinetics ◽  
Flip Chip ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Balls ◽  
Free Solder ◽  
Kinetics Of Reaction ◽  
Kinetics Of

Evaluation of Cu/Sn-Cu Bump Bonding Processes for 3D Integration Using a Fluxing Adhesive

2010 ◽  
Vol 7 (3) ◽  
pp. 143-145 ◽  
Author(s):  
Alan Huffman ◽  
Christopher Gregory ◽  
Matthew Lueck ◽  
Jason Reed ◽  
Dorota Temple ◽  
...  
Keyword(s):  
Mechanical Strength ◽  
Environmental Protection ◽  
Cross Section ◽  
Sem Analysis ◽  
Electrical Measurements ◽  
3D Integration ◽  
Test Vehicle ◽  
Area Array ◽  
Underfill Material

We present the results of a study to evaluate the use of a fluxing adhesive developed by LORD Corp. in the bonding of Cu/Sn-Cu bump structures for interconnection in 3D integration structures. Using an area-array daisy chain test vehicle with a bump pitch of 25 μm, samples are prepared using our standard bonding methodology and also with the fluxing adhesive and then evaluated through electrical measurements and cross section SEM analysis. The results show that the use of the fluxing underfill material results in a well-formed bond between the Cu and Cu/Sn bumps and encapsulates the interconnects to provide environmental protection and additional mechanical strength to the interconnect array.

Research on Gear Contact Fatigue Stress Test

2011 ◽  
Vol 86 ◽  
pp. 825-828
Author(s):  
Tie Wang ◽  
Hong Mei Li ◽  
Rui Liang Zhang ◽  
Zhi Fei Wu
Keyword(s):  
Damage Accumulation ◽  
Stress Test ◽  
Contact Fatigue ◽  
Test Method ◽  
Fatigue Stress ◽  
Accumulation Curve ◽  
Limit Value ◽  
Fatigue Damage Accumulation ◽  
Gear Contact ◽  
The Cost

This paper put forward the rapid measure method of the gear contact fatigue stress value with a few gear samples, which can get the estimated value of the gear fatigue limit value precisely and rapidly. And the gear fatigue life curve and fatigue damage accumulation curve are simulated by MATLAB. Comparing with the traditional test method, this method can reduce the cost and save the time.

Electromigration in Power Devices

2020 ◽  
Vol 2020 (1) ◽  
pp. 000078-000084
Author(s):  
Hao Zhuang ◽  
Robert Bauer ◽  
Markus Dinkel
Keyword(s):  
Current Density ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Stress Test ◽  
Test System ◽  
Circuit Board ◽  
Power Device ◽  
Current Direction ◽  
Power Devices ◽  
Maximum Current

Abstract In the power semiconductor industry, there is continuous development towards higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~8x for QFN 5×6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger compared to a 100 μm micro-bump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development towards higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5×6 package to study the EM behavior of a power device soldered on a Printed Circuit Board (PCB). We employed the highest current (120 A) and temperature (150 °C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168 °C) than the PCB board which was kept under temperature control at 150 °C. This temperature difference resulted in a thermal gradient between the device and PCB which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the MOSFET chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an accelerated mode and, thus, investigate the pure EM behavior of the power device.

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