Evolution of Prony Parameters for Underfills Subjected to High Temperature Long Term Aging

Advanced drive assist systems and support power systems reside underhood where operating temperatures are much higher than in traditional consumer applications. Temperatures in automotive underhood electronics may range from −40 °C to +150°C for long periods of time during operation. Much of the advanced functionality is enable through the use of advanced architectures including flip-chip ball-grid arrays. Underfills are used to enhance the solder joint reliability between the chip and the substrate. However, there is insufficient information about the viscoelasticity of Underfills stored in sustained high temperature for long period of time. In this paper, two different types of Underfills have been cured and aged under two different temperatures: 100 °C and 150 °C. Multi-frequency scan dynamic mechanical analyzer (DMA) test has been conducted to study the viscoelasticity evolution from pristine, 30 days, 60 days, 90 days and 120 days. The master curve has been obtained and the pony pairs of UFs have been calculated. The linear viscoelastic behavior of two kinds of Underfills as the function of aging time and aging temperature has been investigated. Elastic modulus, loss modulus and glass transition temperature are extracted from the results of dynamic loading tests. The aging effect of linear viscoelasticity has been discussed.

ENEPIG Reliability - Enhancement by Simple Drop in Process Changes

Soldering on ball grid arrays (BGAs) and dense circuit features is standard practice in the microelectronics industry. Key to the success of this operation is solder joint reliability (SJR). The evaluation of solder joint reliability can be satisfied by high speed shear testing (HSS). HSS testing in combination with representative test vehicles are tools that can be used to gain statistical data in order to evaluate the impact of controlled testing. During such a round of controlled testing in the context of a palladium phosphor ENEPIG process, it was observed that the palladium initiation speed and IMC may be related to HSS results. The focus of this paper is not targeting all the optimizations that can lead to high end reliability performance for solderability. This paper will strive to convey steps that are available to all fabricators to maximize High Speed Shear results (HSS). In this paper, it will be shown that soldermask related pinholes can be overcome by implementing a reduction assisted immersion gold bath. This section will also culminate in SJR improvements and stability. The prevention of pin holes is a complicated multifaceted problem. This paper will address the notion that, if pinholes are evident, an enhanced immersion gold bath can be used to overcome serious corrosion. Disturbances in the nickel deposit can be weaknesses that are open for unusual locally aggressive atom exchange between the gold and the nickel that will result is hyper-corrosion. A reduction assisted gold bath is able to mask such areas with controlled deposition. This paper will demonstrate the effectiveness of the optimized, purpose designed, gold bath in overcoming pinhole related corrosion whilst simultaneously scrutinizing the ability of the reduction assisted gold bath to maintain or enhance the reliability expectations that are benchmarked by traditional immersion gold alternatives. During studies it has also been observed that processing is also instrumental in assuring maximum soldering reliability. Whilst rinsing is an accepted procedure, the degree and method of rinsing is often a controversial topic. This is especially true of vertical processes where fluid exchange is replaced by soaking, or in other words agitation neutral, volume related dilution. Environmentally aware practices err on the side of minimal water consumption. This is a requirement that is influenced or selectively amplified by geographical locations. This technical paper will demonstrate that the palladium initiation is crucial if maximum SJR is to be achieved. This experience was gained in association with a significant OEM. Electrochemical and advanced optical techniques will be used to demonstrate that the SJR in terms of HSS can be correlated to palladium initiation and resultant IMC formations. In summary process adjustments can be employed to improve soldering performance and repetition. An optimized reduction assisted gold bath will come together with processing optimizations to provide a data driven overview to convince fabricators that enhancements to their everyday processes exist and can be implemented by drop in solutions. The data that is included should be as interesting to the automotive industry as it is to the emerging substrate like panel industry (SLP).

Lift up! to IC Packaging: Trends and Assembly Reliability

For five decades, the semiconductor industry has distinguished itself from other industries by continuously reducing IC sizes while exponentially increasing functionality (Moore's Law) that enabled IC shrinkage and lower cost. The problem now is that IC shrinkage hit a brick wall, in response, a new paradigm shift is emerged—packaging technologies. Industries now focusing on shrinking the IC packaging through stacking and system integration. This talk presents electronics packaging miniaturization trends from ball grid arrays to wafer level and stack technologies with emphasis on system to package qualification and reliability testing methodologies and results.

Thermal Cycling Study of Quilt Packaging

The continued progress of micro-electronics often requires functionality that is spread across multiple chips. This need has led to the development of a variety of alternative chip-packaging technologies that offer increased speed and bandwidth, with lower losses, in an increasing number of interchip interconnects. One recent alternative is quilt packaging® (QP), which has already shown promise from a performance perspective. The geometry of QP is essentially lateral: large numbers of ultrawide-bandwidth interchip interconnects (superconnects) are made directly by nodules fabricated along the edges of adjacent chips. Metallurgical bonding of the nodules creates a system in the form of a “quilt” of separately manufactured chips. This new interconnect geometry is subject to stresses that are different from more conventional schemes. For example, the thermal stress that causes fatigue and lead to failure in ball grid arrays is essentially shear stress, whereas the most critical stresses in QP are tensile and compressive. This paper describes studies of fatigue failure in QP, with attention to critical high-stress regions previously identified by finite-element modeling. Nodules were fabricated on silicon chips, and both single and quilted chips were thermally cycled up to 1000 times over a range of − 55 °C to 125 °C. Scanning electron microscopy (SEM) was used to detect mechanical failure. Focused-ion-beam cross-sectioning was used to expose the critical interior interfaces of QP structures for SEM examination. QP superconnects were found to be robust under all the test conditions evaluated.

Effects on the Reliability of Lead-Free Solder Joints under Harsh Environment

Pb-free solder joints undergo microstructural and mechanical evolution due to alloy coarsening and growing intermetallic compounds which degrade the joint electrical performance. Electronics assemblies containing solder joints are frequently exposed to elevated temperatures for prolonged periods of time. The purpose of the study is to discover the effect of isothermal aging on the reliability of Sn-Ag-Cu (SAC) assemblies. After studied different surface finishes, we employed Immersion Ag (ImAg), Immersion Sn (ImSn), Electroless Ni/Immersion Au (ENIG) and Electroless Ni/Electroless Pd/Immersion Au (ENEPIG) which have potential for higher reliability and better performance and received increased attention for both packaging and subtracted applications. A full experiment matrix with varying aging temperatures and solder alloys was considered. Package sizes ranged from 19mm, 0.8mm pitch ball grid arrays (BGAs) to 5mm, 0.4mm pitch μBGAs and in additional, 0.65mm MLF and 2512 resistors be particularly tested. Storage condition are temperatures leveling up from 25°C, 55°C, 85°C, 100°C and 125 °C with aging over time periods of 0, 21 days, 6 months, 12 months and 24 months. Afterwards, the specimens all subjected to accelerated thermally cycled from −40°C to 125°C with 15 min dwell times at the high and low peak temperature. The paper presents the experimental data to justify the investigation of the degradation on the characteristic lifetime of SAC alloy on ImAg and ImSn surface finish in elevated temperature environments.