scholarly journals Calculation and validation of thermomechanical stresses in flip chip BGA using the ATC4.2 test vehicle

2003 ◽  
Author(s):  
D.W. Peterson ◽  
S.N. Burchett ◽  
J.N. Sweet ◽  
R.T. Mitchell ◽  
Luu Nguyen
Keyword(s):  
Flip Chip ◽  
Test Vehicle

Molding Recipe Study for MUF Solder Crack Improvement

2018 ◽  
Vol 2018 (1) ◽  
pp. 000121-000124
Author(s):  
Scott Chen ◽  
Leander Liang ◽  
Pallas Hsu ◽  
Tim Tsai ◽  
Mason Liang ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Flow Simulation ◽  
Test Vehicle ◽  
Chip Technology ◽  
Solder Bumps ◽  
Capillary Underfill ◽  
Mold Flow ◽  
Profile Reduction ◽  
Transfer Pressure

Abstract In recent years, flip chip technology becomes more and more important with benefits of thin package profile, reduction of package outline, and excellent electrical and thermal performance by connection of copper pillar bumps (CuP) or C4 solder bumps. In order to fill the die gap to prevent voids problem, two encapsulated solutions could be applied: capillary underfill (CUF) and molded underfill (MUF). In general comparison, CUF means to dispense underfill first to fill in die gap then proceed over-molding afterward; and MUF is directly fill under and above die by mold compound. The advantages of MUF solution are low cost and high throughput, however, it will suffer other assembly issues such as solder extrusion and solder crack, and might result in potential function failure. To form these kinds of defects, we suspected that solder will plastically deform under thermal stress treatment, which comes from unbalance mold transfer pressure and material expansion stress during thermal process. In this article, we have tried to investigate the mechanism of solder crack through molding recipe DOE (Design of Experiment) and mold flow simulation. The test vehicle is 12 × 12 mm2 FCCSP, with 6 × 5 mm2 die size. The bump type is copper pillar bump and pitch/size are 126 um and 35 × 60 um2, respectively. The molding recipe has been evaluated by cross section, and it revealed that molding transfer time and molding temperature are directions toward improvement of solder crack issue.

Use of Wafer Applied Underfill for 3D Stacking

2011 ◽  
Vol 2011 (1) ◽  
pp. 000008-000016 ◽  
Author(s):  
Antonio La Manna ◽  
K. J. Rebibis ◽  
C. Gerets ◽  
E. Beyne
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Initial Assessment ◽  
Test Vehicle ◽  
Differential Movement ◽  
The Right ◽  
3D Stacking ◽  
Material Uniformity ◽  
Work Done

A key element for improving 3D stacking reliability is the choice of the right Underfill materials. The Underfill is a specialized adhesive that has the main purposes of locking top and bottom dies; it must fill the gap between bumps and between dies, while reducing the differential movement that would occur during thermal cycling. Traditional underfill processes are based on local dispensing after solder bump reflow (Capillary dispensing), or before flip chip operation with no need of reflow (No Flow Underfill, NUF). In case of 3D stacking, such processes present some limitations: need of a dispensing area (die size increase); material flowing (spacing between dies) and cost (low throughput). After an introduction on typical underfill applications like die-to-package and die-die assembly, we report the work done to assess the properties of several Wafer Applied Underfill (WAUF) materials and their integration in 3D stacking. These materials have been initially applied on silicon wafers in order to assess the minimum achievable thickness and the material uniformity. The wafers have been coated by using different methods: spin coating and film lamination. After this initial assessment, the most promising materials have been used for 3D stacking. The test vehicle used has Cu/Sn μbumps with a pitch of 40μm. The quality of the materials is judged by electrical test, SAM (Surface Acoustic Microscope) and X-SEM (Scanning Electron Microscope).

Design and Direct Assembly of 2.5D/3D Rigid Silicon Interposer on PCB

2014 ◽  
Vol 2014 (1) ◽  
pp. 000783-000786 ◽  
Author(s):  
Farhang Yazdani
Keyword(s):  
Flip Chip ◽  
Thermal Stresses ◽  
Stress Test ◽  
Temperature Cycle ◽  
3D Integration ◽  
Test Vehicle ◽  
Direct Assembly ◽  
Solder Balls ◽  
Present Design ◽  
The Cost

Silicon interposer is emerging as a vehicle for integrating dies with sub 50um bump pitch in 2.5D/3D configuration. Benefits of 2.5D/3D integration are well explained in the literature, however, cost and reliability is a major concern especially with the increase in interposer size. Among the challenges, reliability issues such as warpage, cracks and thermal-stresses must be managed, in addition, multi-layer build-up flip chip substrate cost and its impact on the overall yield must be considered. Because of these challenges, 2.5D/3D silicon interposer has developed a reputation as a costly process. To overcome the reliability challenges and cost associated with typical thin interposer manufacturing and assembly, a rigid silicon interposer type structure is disclosed. In this study, interposer with thickness of greater than 300um is referred to as rigid interposer. Rigid silicon interposer is directly assembled on PCB without the need for intermediary substrate. This eliminates the need for an intermediary substrate, thin wafer handling, wafer bonding/debonding procedures and Through Silicon Via (TSV) reveal processes, thus, substantially reducing the cost of 2.5D/3D integrated products while improving reliability. A 10X10mm2 rigid silicon interposer test vehicle with 310um thickness was designed and fabricated. BGA side of the interposer with 1mm ball pitch was bumped with eutectic solder balls through a reflow process. Interposer was then assembled on a 50X50mm2 FR-4 PCB. We present design and direct assembly of the rigid silicon interposer on PCB followed by temperature cycle results using CSAM images at 250, 500, 750 and 1000 cycles. It is shown that all samples successfully passed the temperature cycle stress test.

Flip Chip Thermal Test Vehicle Design: Requirements, Evaluations, and Validations

2003 ◽  
Author(s):  
Teck Joo Goh ◽  
Chia-Pin Chiu ◽  
K. N. Seetharamu ◽  
G. A. Quadir ◽  
Z. A. Zainal
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Thermal Characterization ◽  
Circuit Board ◽  
Vehicle Design ◽  
Test Chip ◽  
Test Vehicle ◽  
Design Processes ◽  
Thermal Test ◽  
Design Requirements

This paper reviews the design of a flip chip thermal test vehicle. Design requirements for different applications such as thermal characterization, assembly process optimization, and product burn-in simulation are outlined. The design processes of different thermal test chip structures including the temperature sensor and passive heaters are described in detail. In addition, the design of fireball heater, a novel test chip structure used for evaluating the effectiveness of heat spreading of advanced thermal solutions, is also illustrated. The design considerations and processes of the package substrate and printed circuit board with special emphasis on the physical routing of the thermal test chip structures are described. These design processes are supported with thermal data from various finite-element analyses (FEA) carried out to evaluate the capability and limitations of thermal test vehicle design. Design optimization as the outcome of these analyses is also elaborated. Lastly, the validation and calibration procedures of the thermal test vehicle are presented in this paper.

An Efficient Bump Pad Design to Mitigate the Flip Chip Package Induced Stress

2015 ◽  
Author(s):  
Mario Gonzalez ◽  
Joeri De Vos ◽  
Geert Van der Plas ◽  
Eric Beyne
Keyword(s):  
Buffer Layer ◽  
Flip Chip ◽  
Finite Element Models ◽  
Test Vehicle ◽  
Solder Interconnection ◽  
Geometric Configurations ◽  
Induced Stresses ◽  
Reliability Of Solder Joints ◽  
Stress Buffer ◽  
Time Decrease

A numerical analysis using Finite Element Models of different stress buffer configurations has been proposed for improving the reliability of solder joints and at the same time decrease the induced stresses in the back-end-of-line (BEOL). A non-underfilled Flip Chip with a silicon die size of 10×10 mm2 mounted on a FR4 board has been used as test vehicle. The die to substrate interconnection is done by using copper pillars and Sn solder with a diameter of 50 μm and a total standoff of 50 μm. The thickness of the passivation, a copper pedestal fabricated as a redistribution I/O pad and a polymeric buffer layer with different geometric configurations were used in combination to minimize the induced stresses in the BEOL and increase the flexibility of the copper pillar interconnections. It was found that a stiff layer below the copper pillar has the major contribution to reduce the stress in the BEOL, while the softer buffer layer minimizes the induced plastic strain in the solder interconnection. Fabrication of the samples with optimal configuration are under progress.

Flip Chip Process Development and Relaibility Evaluation With Lead-Free Solder Alloy

2002 ◽  
Author(s):  
Mohammad Yunus ◽  
Muthiah Venkateswaran ◽  
Peter Borgesen
Keyword(s):  
Flip Chip ◽  
Process Development ◽  
Alpha Particles ◽  
Development Effort ◽  
Test Vehicle ◽  
Initial Development ◽  
Electronic Products ◽  
Semiconductor Chip ◽  
Cu Alloy ◽  
Free Solder

Usually, flipchip technology is based on either high-Pb or eutectic Sn/Pb solder forming the connections between the semiconductor chip and the carrier substrate. However decay of the 210Pb constituent, via 210Bi and 210Po, to 206Pb involves the emission of energetic alpha particles which have a tendency to cause soft errors in nearby active elements on the chip. Also, impending legislations in Europe and Japan on the elimination of Pb from electronic products have prompted the investigation of alternative solder alloys. This paper outlines an initial development effort focussed on the Sn/Ag/Cu (95.8/3.5/0.7) alloy. The study involved the development of a flip chip assembly process followed by a reliability evaluation comparing the fatigue resistance of the Sn/Ag/Cu alloy to that of eutectic Sn/Pb solder. The test vehicle used was a 225μm bump pitch, 11mm square die mounted on a ceramic substrate.

Addressing Failures in Advanced Packaging Through a Correlative Workflow

2020 ◽  
Author(s):  
Neel Leslie ◽  
Brian Lai ◽  
Heebeom Lee ◽  
Mingi Lee ◽  
Christopher H. Kang ◽  
...  
Keyword(s):  
Cross Section ◽  
Fault Location ◽  
Flip Chip ◽  
Fault Isolation ◽  
High Confidence ◽  
Test Vehicle ◽  
Surface Charging ◽  
Analysis Workflow ◽  
Defect Isolation ◽  
Advanced Packaging

Abstract Correlation across applications and imaging platforms is essential and brings increased insurance for fault isolation in advance of destructive imaging. This paper demonstrates an approach for a detailed advanced packaging defect isolation and analysis workflow. To determine the effectiveness of the proposed workflow, a 28nm flip-chip was used as a test vehicle. By using this workflow, the yield in determining the fault location has increased from 60% to over 85%. To further improve the result, a surface charging mitigation scheme was used and the resulting measured correlative offset between the two systems was found to be less than 10um. This creates novel opportunities in reducing the size of the cross-section and increasing the overall throughput to find the defect, with high confidence. This workflow creates unique abilities in fault localization and analysis as it can detect both opens and shorts between the different techniques that are employed.

Next Gen Test-Vehicle to Simulate Thermal Load for IoT FPGA Applications

2018 ◽  
Author(s):  
Suresh Parameswaran ◽  
Gamal Refai-Ahmed ◽  
Suresh Ramalingam ◽  
Boon Ang
Keyword(s):  
Power Dissipation ◽  
Evaluation System ◽  
Flip Chip ◽  
Semiconductor Device ◽  
Thermal Interface Material ◽  
Feature Size ◽  
Test Vehicle ◽  
Circuit Performance ◽  
Development Cycle ◽  
Size Scales

As semiconductor device feature size scales and circuit performance increases, power dissipation and thermal management are becoming very important. Attention to thermal considerations is required throughout the chip development cycle from preliminary architecture planning to deployment on customer board and beyond. This paper describes a versatile thermal test vehicle that can be used to address these requirements. We discuss the architecture and implementation of a specially designed test-vehicle chip, followed by its operation. The programmability and flexibility of this vehicle will be highlighted. In addition, we cover other usage of this vehicle which includes modelling of chip-level thermal behavior with different floorplan, simulating thermal loads in IoT FPGA applications, cross-calibrating thermal numerical simulators with measured silicon data and evaluating the thermal impact of different package form-factor / material (such as thermal interface material) and cooling solutions. The abovementioned chip was fabricated using 0.18um technology and assembled in a flip-chip package. The reminder of this evaluation system is a simple, inexpensive tester from which a software is run to program the chip and to measure the spatial & temporal temperature values. Measured thermal data from different use cases are presented in this paper.

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