Thermal Interface Material Technology Advancements and Challenges: An Overview

2005 ◽  
Author(s):  
Ashay Dani ◽  
James C. Matayabas ◽  
Paul Koning
Keyword(s):  
Flip Chip ◽  
Phase Change Materials ◽  
Heat Dissipation ◽  
Low Cost ◽  
Thermal Interface Material ◽  
Next Generation ◽  
Material Technology ◽  
Thermal Interface ◽  
Flip Chip Packaging ◽  
Architecture And Design

With an increase in the number of transistors (higher power), shrinking processor size (smaller die), and increasing clock speeds (higher frequency) for next generation microprocessors, heat dissipation at the silicon die level has become a critical focus area for microprocessor architecture and design. In addition, power removal at low cost continues to remain the key challenge as we develop the next generation packaging technologies. Novel Thermal Interface Materials (TIM) are required to be designed and developed to meet these new package thermal targets. This paper presents an overview of the novel TIM technologies developed at Intel including greases, phase change materials (PCM), gels, polymer solder hybrids, and solder TIM for multiple generations of desktop, server and mobile microprocessors. The advantages and limitations of these TIM technologies in the thermal management of flip chip packaging are reviewed for Intel’s microprocessors.

Effects of Thermal Lids Gold Plating Thickness on Thermal Interface Reliability for Flip Chip Packaging

2007 ◽  
Author(s):  
Chin Hock Toh ◽  
Arun Raman ◽  
Thomas Fitzgerald ◽  
Madhuri Narkhede ◽  
Alfred A. La Mar ◽  
...  
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Temperature Cycling ◽  
Thermal Interface Material ◽  
Thermal Impedance ◽  
Thermal Reliability ◽  
Gold Plating ◽  
Thermal Interface ◽  
Density Values ◽  
Flip Chip Packaging

This paper summarizes the intermetallic compounds (IMC) formation at the interface between thermal interface material (TIM) and nickel/gold plated integrated heat spreader (IHS) at varying Au thickness, and its impact on thermal reliability. Indium solders due to their high thermal conductivity are commonly used as the TIM to dissipate heat from silicon die to the thermal lids for new generation microprocessors with higher operating die temperatures. Indium solders readily wet the Au plating on thermal lids to form IMC during soldering. Optimal Au thickness is essential; Au thickness should be thick enough for reliable soldering, but must also be thin enough to offset the high cost and to prevent formation of a brittle Au-rich IMC layer in the solder joint. AuIn2 is the preferred IMC for indium-gold soldering and does not embrittle the solder joint. Resulting IMC type depends on the Au:In ratio which can be predicted by a In-Au binary phase diagram. On this basis, critical Au plating thickness to form AuIn2 IMC can be estimated using the known density values for electroplated gold and indium. In this study, Au thicknesses ranging from 0.035 to 0.2μm with a fixed gold pad size were electrolytically plated on a nickel plated copper lid. Assembled units were then subjected to Temperature Cycling-B (TCB). An in-house developed metrology for measuring junction-to-case thermal impedance (Rjc) is described. In this study, varying the thermal lids Au-plating thickness between 0.035 to 0.2 μm only lead to slight increase in center and corner Rjc values through 115 cycles TCB. The maximum center Rjc degradation post thermal cycling observed was only ∼ 1.7% on the lids with Au pad thickness between 0.035 – 0.04 μm. There were also no clear indications of impact of Au pad thickness on center and corner Rjc performance at EOL or post 115 cycles TCB. Thermal lids/TIM interface integrity remains unchanged for the range of Au pad thickness considered. However, detailed scanning electron microscopy and energy dispersive spectroscopy showed thicker Au plating results in greater incidence of AuIn2 IMC nodules beneath In-Ni-Au ternary IMC layer at end of line (EOL) ie post packaging and test. AuIn2 IMC is formed right after assembly and is what that holds the solder to the lid. As such, it follows that the presence of a more continuous and possibly greater number of AuIn2 IMC nodules can be expected to provide a better lid-solder joint at EOL.

Prospects for automotive SiP modules applying IC assembly and packaging technology

2019 ◽  
Vol 2019 (1) ◽  
pp. 000006-000012
Author(s):  
Tomohiro Furukawa ◽  
Takahiro Kasuga ◽  
Masato Umehara ◽  
Yuka Tamadate
Keyword(s):  
Flip Chip ◽  
Heat Dissipation ◽  
Coefficient Of Thermal Expansion ◽  
Thermal Interface Material ◽  
Heat Sources ◽  
Heat Spreader ◽  
Thermal Interface ◽  
Passive Components ◽  
Reflow Temperature ◽  
Assembly Technology

Abstract We develop a package that ensures quality complying with AEC-Q 100 Grade 2 which is in-vehicle quality from various flip chip mounting methods and bump sealing technology with underfill resin and mold resin. FC CSP with heat spreader mounted on the product which has started mass production since last year is in the lineup, The heat dissipation can be improved by attaching the heat spreader directly to the chip backside which are heat sources and the Thermal Interface Material (TIM), using our assembly technology of flip chip mounting and molding the periphery while exposing the chip backside. By adjusting the Coefficient of Thermal Expansion (CTE) and thickness of the material, we realize low warpage and low coplanarity at reflow temperature and product use temperature environment and reduce package displacement behavior, we will improve the secondary mountability to the motherboard and provide reliable packages. Furthermore, it can be applied to SiP modules. It is also possible to construct multiple chip modules by mounting multiple ICs or placing low-passive components around them. We will consider heat spreader mounting on multiple ICs that generate heat, and metal coating on the entire SiP module to have a structure that achieves both heat dissipation and electromagnetic shielding as a future idea.

Metal Thermal Interface Material for the Next Generation FCBGA

2021 ◽  
Author(s):  
YunAh Kim ◽  
JoHyun Bae ◽  
HyunHye Jung ◽  
MiKyoung Choi ◽  
YoungDo Kweon ◽  
...  
Keyword(s):  
Thermal Interface Material ◽  
Next Generation ◽  
Thermal Interface

A HIGH THROUGHPUT, LOW COST ASSEMBLY APPROACH FOR LED IMS PACKAGES TO HEAT SINK USING ADVANCED THERMAL INTERFACE MATERIALS

2015 ◽  
Vol 2015 (1) ◽  
pp. 000627-000632 ◽  
Author(s):  
Swapan K. Bhattacharya ◽  
Fei Xie ◽  
Han Wu ◽  
Kelley Hodge ◽  
Keck Pathammavong ◽  
...  
Keyword(s):  
Heat Sink ◽  
High Performance ◽  
High Reliability ◽  
Low Cost ◽  
Thermal Interface Material ◽  
Thermal Interface Materials ◽  
Thermal Interface ◽  
Cycle Times ◽  
High Adhesion ◽  
Machine Cycle

The objective of this study is to design and fabricate a high reliability LED Insulated Metal Substrate (IMS) package to complex heat sink attachment using an advanced thermal interface material (TIM). The assembly consists of LED IMS parts bonded to a heat spreader/sink using an advanced TIM and a corner bond material to quickly and accurately secure the LEDs in position. The corner bond adhesive is snap cured for fast machine cycle times while the high performance, high adhesion TIM materials cure throughout the rest of the assembly operation. This approach allows high accuracy LED bonding without the need for alignment pins or fasteners to anchor to the IMS. The IMS attached to the heat sink is then electrically interconnected with a thin flex substrate on top of the IMS. This approach is expected to replace the current mechanical fastners and low strength silicone TIM materials and reduce the cycle time and overall placement cost which are key drivers especially for the automotive industry.

Evaluation of Bare Die Chip Reliability Due to Underfill Materials During Mechanical Actuation and Thermal Cycling

2005 ◽  
Author(s):  
Arv Sinha
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Bond Line ◽  
Thermal Interface Material ◽  
High Power Density ◽  
The Finite Element Method ◽  
Chip Design ◽  
Thermal Interface ◽  
Ball Grid Arrays ◽  
Mechanical Actuation

Use of underfill materials to encapsulate ball grid arrays (BGAs) or chip scale packages (CSPs) have become very important in increasing the reliability of area array packages [1]. Underfill enhances the reliability of flip-chip devices by distributing the thermo-mechanical stresses [2, 3]. These stresses are generated due to mechanical actuation and coefficient of thermal expansion mismatch (CTE) [3]. They are required due to high power density of the current chip design to achieve fine bond line at the thermal interface material in order to dissipate heat. In this paper, details of reliability assessment using the finite element method and actual test data will be presented and discussed.

Bump Electromigration and Back End Design Rules

2007 ◽  
Author(s):  
Vishal Nagaraj ◽  
Saket Karajgikar ◽  
Dereje Agonafer ◽  
Senol Pekin
Keyword(s):  
Flip Chip ◽  
Heat Dissipation ◽  
High Current Density ◽  
Electrical Performance ◽  
High Current ◽  
Current Crowding ◽  
Element Analysis ◽  
Chip Technology ◽  
Flip Chip Packaging ◽  
Current Densities

As there is continuous demand for miniaturization of electronic devices, flip chip technology is predominantly used for high density packaging. The technology offers several advantages like excellent electrical performance and better heat dissipation ability. Original invention of flip chip packaging utilized ceramic substrates and high lead bumps. Low cost commercialization of this packaging technology, however, required organic laminate substrates coupled with SnPb eutectic bumped interconnects on the die side. While organic laminate flip chip packaging may be a good option for many low power applications, current carrying capability of the eutectic bumped interconnect causes a catastrophic failure mechanism called electromigration. Previously, researchers have identified and addressed few issues regarding electromigration. Electomigration leads to the formation of metal voids in the conductors which eventually increases the resistance drop across the conductor causing electrical opens. Electromigration is very significant at high current densities. Temperature is the other parameter of concern for electromigration. High current density causes temperature to rise due to Joule heating, there by reducing the life of package. In order to determine the factors responsible for high current densities, we formed a full factorial design of experiments (DOE) that contained parameters such as passivation opening, UBM size, UBM thickness and trace width. Finite Element Analysis (FEA) was performed in order to study the effect of above parameters on current crowding and temperature in the bumped interconnects. Based on the results, hierarchy of the most important parameters to be considered while selecting the appropriate flip chip technology is proposed.

Thermal Resistance Analysis of Sn-Bi Solder Paste Used as Thermal Interface Material for Power Electronics Applications

2014 ◽  
Vol 136 (1) ◽  
Author(s):  
Rui Zhang ◽  
Jian Cai ◽  
Qian Wang ◽  
Jingwei Li ◽  
Yang Hu ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
Power Electronics ◽  
Heat Dissipation ◽  
Laser Flash ◽  
Acoustic Microscopy ◽  
Thermal Interface Material ◽  
Solder Paste ◽  
Good Reliability ◽  
Thermal Interface ◽  
Power Modules

To promote heat dissipation in power electronics, we investigated the thermal conduction performance of Sn-Bi solder paste between two Cu plates. We measured the thermal resistance of Sn-Bi solder paste used as thermal interface material (TIM) by laser flash technique, and a thermal resistance less than 5 mm2 K/W was achieved for the Sn-Bi TIM. The Sn-Bi solder also showed a good reliability in terms of thermal resistance after thermal cycling, indicating that it can be a promising candidate for the TIM used for power electronics applications. In addition, we estimated the contact thermal resistance at the interface between the Sn-Bi solder and the Cu plate with the assistance of scanning acoustic microscopy. The experimental data showed that Sn-Bi solder paste could be a promising adhesive material used to attach power modules especially with a large size on the heat sink.

scholarly journals Thermal Performance of LED Filament in Flip-Chip Packaging Manufactured for Different Correlated Color Temperature

2021 ◽  
Vol 11 (19) ◽  
pp. 8844
Author(s):  
He Jiang ◽  
Jiming Sa ◽  
Cong Fan ◽  
Yiwen Zhou ◽  
Hanwen Gu ◽  
...  
Keyword(s):  
Thermal Performance ◽  
Flip Chip ◽  
Heat Dissipation ◽  
Light Emitting Diode ◽  
Color Difference ◽  
Junction Temperature ◽  
Color Temperature ◽  
Constant Current ◽  
Light Emitting ◽  
Flip Chip Packaging

The effect of correlated color temperature (CCT) on the thermal performance of light emitting diode (LED) filament in flip-chip packaging was investigated in detail. Two filaments with different lengths were selected as the research object, and the thermal resistance of filaments under three CCT (2200 K, 2400 K, 2700 K) were studied. The optical properties and thermal parameters of the two groups of filaments were measured, and the results were analyzed combined with the color coordinate. The experimental results show that thermal properties of LED filaments is closely related to CCT. Under constant current condition, junction temperature decreases with the increase of color difference. With the change of phosphor glue and phosphorus powder ratio, the color temperature of LED filament also changes. In the filaments with the same chip structure and packaging mechanism, the higher the proportion of red phosphorescent powder, the worse the heat dissipation performance of the filament. These results show that in the design and manufacture of LED filament, it is helpful to control the CCT of LED filament under the premise of meeting the use requirements.

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