Cu pillars on substrates — a low cost alternative for the next generation of Flip Chip packaging technology

2010 ◽  
Author(s):  
D. Gupta ◽  
H. Sato ◽  
Y. Nakadaira
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Next Generation ◽  
Packaging Technology ◽  
Flip Chip Packaging

Thermal Interface Material Technology Advancements and Challenges: An Overview

2005 ◽  
Author(s):  
Ashay Dani ◽  
James C. Matayabas ◽  
Paul Koning
Keyword(s):  
Flip Chip ◽  
Phase Change Materials ◽  
Heat Dissipation ◽  
Low Cost ◽  
Thermal Interface Material ◽  
Next Generation ◽  
Material Technology ◽  
Thermal Interface ◽  
Flip Chip Packaging ◽  
Architecture And Design

With an increase in the number of transistors (higher power), shrinking processor size (smaller die), and increasing clock speeds (higher frequency) for next generation microprocessors, heat dissipation at the silicon die level has become a critical focus area for microprocessor architecture and design. In addition, power removal at low cost continues to remain the key challenge as we develop the next generation packaging technologies. Novel Thermal Interface Materials (TIM) are required to be designed and developed to meet these new package thermal targets. This paper presents an overview of the novel TIM technologies developed at Intel including greases, phase change materials (PCM), gels, polymer solder hybrids, and solder TIM for multiple generations of desktop, server and mobile microprocessors. The advantages and limitations of these TIM technologies in the thermal management of flip chip packaging are reviewed for Intel’s microprocessors.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

Next-Generation Copper, Nickel and Lead-Free Metallization Products for Next-Generation Devices and Applications

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000611-000638
Author(s):  
Jonathan Prange ◽  
Yi Qin ◽  
Matthew Thorseth ◽  
Inho Lee ◽  
Masaaki Imanari ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Lead Free ◽  
Lead Free Solder ◽  
Next Generation ◽  
Copper Nickel ◽  
Microelectronic Devices ◽  
Architectural Features ◽  
Free Solder

Flip-chip interconnect and 3-D packaging applications must utilize reliable, high-performance metallization products in order to produce highly-efficient, low-cost microelectronic devices. As the market moves to shrinking device architectural features and increasingly difficult pattern layouts, more demand is placed on the plating performance of the copper, nickel and lead-free solder products used to create these interconnects. Additionally, the move from traditional C4 bumping processes with lead-free solder to capping processes utilizing copper pillars with lead-free solder requires metal interfaces that are highly compatible in order to avoid defects that could occur. In this paper, next-generation products developed for copper pillar, nickel barrier, and lead-free solder plating will be introduced that are capable of delivering high-performance and highly reliable metallic interconnects. The additive packages that were selected and optimized allowing for increased rate of electrodeposition, uniform height control with controllable pillar shape and smooth surface morphology will be discussed. Furthermore, compatibility will be shown for a lead-free solder cap electrodeposited onto copper pillar structures, both with and without nickel barrier layers, on large pore features (≥50 μm diameter) and micro pore features (≤20 μm diameter) for both bumping and capping applications.

Improvement of ELK Reliability in Flip Chip Packages using Bond-on-Lead (BOL) Interconnect Structure

2010 ◽  
Vol 2010 (1) ◽  
pp. 000197-000203 ◽  
Author(s):  
Eric Ouyang ◽  
MyoungSu Chae ◽  
Seng Guan Chow ◽  
Roger Emigh ◽  
Mukul Joshi ◽  
...  
Keyword(s):  
Finite Element ◽  
Flip Chip ◽  
Low Cost ◽  
Reliability Testing ◽  
Element Simulation ◽  
Testing Data ◽  
Flip Chip Packaging ◽  
Solder Mask ◽  
The Cost ◽  
Low K

In this paper, a novel flip chip interconnect structure called Bond-On-Lead (BOL) and its ability to reduce stress in the sensitive sub-surface ELK (Extra Low K) layers of the die is presented. BOL is a new low cost flip chip packaging solution which was developed by STATSChipPAC to dramatically reduce the cost of flip chip packaging. The BOL solution allows for efficient substrate routing by virtue of the use of narrow BOL pads and the removal of solder mask in the area of the BOL pads, which eliminates the limitations associated with solder mask opening sizes and positional tolerances. In addition to the compelling cost benefits, modeling results are confirmed with empirical reliability testing data to show that BOL is superior to the traditional Bond-on-Capture Pad (BOC) configuration from a mechanical stress and reliability perspective. The focus of this paper is on the theoretical analysis of the stress, strain, and warpage associated with the BOL configuration compared with the traditional BOC structure. For the package deformation, the global finite element method is used to simulate the package warpage. For the local bumping reliability, the focus is on the ELK layers which are the critical locations affecting the package's reliability. The local finite element simulation is conducted to compare the critical ELK layers stresses with BOL structure vs. with traditional BOC structure.

Sign in / Sign up

Export Citation Format

Share Document