Enhanced Processability and Thermal Fatigue Reliability With Low Melting Point SnBi Solder Alloy LMPA-Q

SnBi based solder alloys become an interesting alternative for standard SnAgCu as they can be used to solder components at much lower temperature. The typically 50°C lower solder reflow temperature is less damaging for PCB and components, and also prevents hot tear and head-in-pillow failures for large fine pitch BGA components. A reasonable concern for these low-melting temperature solders is the thermal cycling reliability performance, in particular for harsh conditions such as automotive products. In this work, thermal cycling testing and failure analysis have been performed on 9 × 9 mm size QFN components and large chip components (2010 and 2512) which are typically sensitive to thermal fatigue. The results are benchmarked to standard SAC alloy. Also the process advantages from the low temperature solder alloys are depicted in this paper. Finally, the effect of Pb contamination on this SnBi based solder is investigated.

Dynamic warpage simulation of molded PCB under reflow process

Purpose This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage behavior for different form factor sizes. Design/methodology/approach This study analyzes warpage during the reflow process. The shadow moiré experiment methodology is used to collect data on the dynamic warpage performance of a model with a form factor of 10mm × 10mm × 1mm. The temperature profile with heating from 25°C to 300°C at intervals of 50°C is used, and the sample is made to undergo a cooling process until it reaches the room temperature. Subsequently, ANSYS static structural simulation is performed on similar form factor models to ascertain the accuracy of the simulation results. Findings Results show that the deformation and total force induced by coefficient of thermal expansion (CTE) mismatch are examined based on the warpage performance of models with different sizes, that is, 45mm × 45mm × 1mm and 45mm × 15mm × 1mm. Compared with the experimental data, the simulated modeling accuracy yields a less than 5% deviation in the dynamic warpage prediction at a reflow temperature of 300°C. Results also reveal that the larger the model, the larger the warpage changes under the reflow temperature. Research limitations/implications The simulated warpage is limited to the temperature and force induced by CTE mismatch between two materials. The form factor of the ball-grid array model is limited to only three different sizes. The model is assumed to be steady, isothermal and static. The simulation adopts homogenous materials, as it cannot accurately model nonhomogeneous multilayered composite materials. Practical implications This study can provide engineers and researchers with a profound understanding of molded PCB warpage, minimal resource utilization and the improved product development process. Social implications The accurate prediction of molded PCB warpage can enable efficient product development and reduce resources and production time, thereby creating a sustainable environment. Originality/value The literature review points out that warpage in various types of PCBs was successfully examined, and that considerable efforts were exerted to investigate warpage reduction in PCB modules. However, PCB warpage studies are limited to bare PCBs. To the best of the authors’ knowledge, the examination of warpage in a molded PCB designed with a molded compound cover, as depicted in Figure 3, is yet to be conducted. A molded compound provides strong lattice support for PCBs to prevent deformation during the reflow process, which is a topic of considerable interest and should be explored.

Strength and Isothermal Fatigue Resistance of Snbi/snagcu Joints Reflowed At Low Temperatures

Soldered microelectronics assemblies may have to survive a variety of mechanical loads in repeated drops, cyclic bending, or vibration. A very large body of work has addressed the isothermal fatigue performance of SnAgCu solder joints. The present work offers a general assessment of the achievable performance of so-called hybrid solder joints formed by soldering with eutectic SnBi or SnBiAg to SnAgCu bumps on area array components. This allows for soldering at much lower temperatures than with SnAgCu alone, but the deformation and damage properties of the resulting structures depend strongly on details of the design and process. A peak reflow temperature of 175C was shown to be sufficient to ensure that the life of the joints remains limited by fatigue of the unmixed SnAgCu near the component. However, a higher effective stiffness of the mixed region near the substrate means that the life will be lower by 45%.

Understanding Package Delamination through Package Deformation Modeling at Different Thermal Conditions

Package delamination is one of the problems in semiconductor packaging. Understanding the delamination mechanism in a specific situation is very important to identify the root cause and implement robust solution. In this study, package deformation modeling was done to analyze the deformation of the substrate or package at different thermal conditions. The modeling result was compared with the actual package deformation of the package with delamination problem. It was found out that the observed deformation through actual cross-section analysis matched with the modeling result at reflow temperature condition. Thus, it could be concluded that the delamination happens during package reflow and not after post mold cure or the preceding processes.

STUDYING THE POSSIBILITY OF USING COLEMANIT TO OBTAIN ENAMELS ON STEEL

The practical use of boron and its compounds is extremely diverse due to its different properties. About 55 % of boron raw materials are consumed by the glass and ceramic industries for the manufacture of optical glasses, heat-insulating glass fibers, acid-resistant and refractory products, enamels, glazes, porcelain, etc. The paper considers the possibility of using colemanite to obtain enamel over steel. The optimal temperature-time regime of firing has been developed to obtain a high-quality coating and achieve the desired effect. It has been established that colemanite can partially replace cover enamel drill. On the basis of the studies carried out, it was found that the obtained experimental enamel is more refractory than the ESP-210 enamel. The optimal firing temperature for the experimental coating was established – 950 ° С, for the ESP-210 coating – 825 ° С. For uniform reflow of the experimental coating, a temperature is required that exceeds the reflow temperature of ESP-210 by 125 ° C. Colemanite-containing batch was cooked. Cooking was carried out in an electric oven at 1300 ° C for 5 hours. For further research, a slip was prepared from the experimental enamel and applied by pouring onto the plates

Prospects for automotive SiP modules applying IC assembly and packaging technology

We develop a package that ensures quality complying with AEC-Q 100 Grade 2 which is in-vehicle quality from various flip chip mounting methods and bump sealing technology with underfill resin and mold resin. FC CSP with heat spreader mounted on the product which has started mass production since last year is in the lineup, The heat dissipation can be improved by attaching the heat spreader directly to the chip backside which are heat sources and the Thermal Interface Material (TIM), using our assembly technology of flip chip mounting and molding the periphery while exposing the chip backside. By adjusting the Coefficient of Thermal Expansion (CTE) and thickness of the material, we realize low warpage and low coplanarity at reflow temperature and product use temperature environment and reduce package displacement behavior, we will improve the secondary mountability to the motherboard and provide reliable packages. Furthermore, it can be applied to SiP modules. It is also possible to construct multiple chip modules by mounting multiple ICs or placing low-passive components around them. We will consider heat spreader mounting on multiple ICs that generate heat, and metal coating on the entire SiP module to have a structure that achieves both heat dissipation and electromagnetic shielding as a future idea.

STUDY OF Co/Sn MULTILAYER SYSTEM WITH VARIOUS TIN LAYER THICKNESS AND REFLOW TEMPERATURES

Co–Sn–Co multi-layer films with various Sn-layer thicknesses have been deposited by using the electrodeposition technique. The deposition was performed at room temperature on gold coated silicon substrates. The thickness of Sn layer was kept [Formula: see text]4.5, 2.5, 1.5 and 1[Formula: see text][Formula: see text]m, while the thickness of each Co layer was fixed to [Formula: see text]0.75[Formula: see text][Formula: see text]m. The Sn layer was sandwiched between two Co layers. The total thickness of the films was [Formula: see text]6, 4, 3, 2.5[Formula: see text][Formula: see text]m, respectively. The intended ratio of Sn was about 25 at.% while Co was about 75 at.%. The separation inside the Sn-layer has been observed at higher Sn-layer thicknesses with increasing reflow temperature. It may be due to the combined effect of thermal stress arising during cooling from elevated reflow temperatures and solidification shrinkage in the thick Sn layer due to the formation of IMC CoSn2. However, 1[Formula: see text][Formula: see text]m has been found to be a critical thickness, which remains intact when sandwiched between two cobalt layers. The structure of these multi-layer films was studied as a function of temperature. It has been observed from X-ray diffraction (XRD) that the as-deposited films exhibit strong peaks belonging to elemental Co and Sn. At temperatures of 270–290∘C, CoSn2 begins to appear and grow at the interfaces and in the middle of Sn layer with the decrease in elemental Sn. However, sufficient amount of Co is still present in pure form as is evident by the XRD and field emission scanning electron microscopy images at all temperatures. This study confirms that only one reaction product, viz. CoSn2, formed in as-deposited during reflow at temperatures 270–290∘C for a fixed time of 10[Formula: see text]min, although several other stable IMCs, e.g. Co3Sn2, CoSn, CoSn2, CoSn3 exist in the Co–Sn system at 250∘C according to phase diagram. It is not uncommon that all the thermodynamically stable IMCs do not form in the system due to kinetic reasons. Accordingly, the formation of IMCs through interfacial reaction has been discussed in this paper.

Reliability Analysis of a Wearable Sensor Patch (WSP) to Monitor ECG Signals

Flexible Hybrid Electronic (FHE) devices interface flexible sensors and circuits with conventional rigid electronic components. This work reports preliminary results for the reliability aspects of a project aimed at fabricating a Wearable Sensor Patch (WSP) to monitor ECG signals. The device was fabricated by interfacing flexible electroplated Cu circuit lines and an ECG sensor on a Kapton® polyimide (PI) substrate with rigid electronics connected using SnPb solder (reflow temperature: 204 °C), making it a FHE device. Phase I of this project faced reliability issues as Cu circuit lines were susceptible to failure due to cracking near the front-end signal conditioning chip. This issue needed to be resolved in Phase II of the project to produce a robust device fit to be used in real world applications. The effect of changes in Cu trace thickness (2 and 6 μm) and Kapton® PI thickness (2 and 5 mil) on device robustness was tested. Effect of the use of low reflow temperature SnBi solder (reflow temperature: 175 °C) on device reliability was also tested. Multiple devices fabricated using different configurations of Cu trace and Kapton® PI thicknesses and either SnPb or SnBi solder were bend tested to single out the most robust configuration. Improved solder pad design for Cu traces at solder joint sites was also tested. It was observed that only devices with 6 μm thick Cu traces, 2 mil thick Kapton® and SnBi solder had no defects as a result of thermal cycling during fabrication. They also performed best during bend testing. Some of the factors contributing to robustness of this configuration might be lower CTE mismatch due to lower solder reflow temperature as well as greater strength under bending due to increased thickness. Improved solder pad design for Cu traces also improved device robustness considerably.