Reliability Analysis of Flip Chip Designs Via Computer Simulation

2000 ◽  
Vol 122 (3) ◽  
pp. 214-219 ◽  
Author(s):  
Hua Lu ◽  
C. Bailey ◽  
M. Cross
Keyword(s):  
Material Properties ◽  
Flip Chip ◽  
Thermal Loading ◽  
Coefficient Of Thermal Expansion ◽  
Empirical Relationship ◽  
Life Time ◽  
Fatigue Reliability ◽  
Chip Design ◽  
Flip Chips ◽  
Out Of Plane

A flip chip component is a silicon chip mounted to a substrate with the active area facing the substrate. This paper presents the results of an investigation into the relationship between a number of important material properties and geometric parameters on the thermal-mechanical fatigue reliability of a standard flip chip design and a flip chip design with the use of microvias. Computer modeling has been used to analyze the mechanical conditions of flip chips under cyclic thermal loading where the Coffin-Manson empirical relationship has been used to predict the life time of the solder interconnects. The material properties and geometry parameters that have been investigated are the Young’s modulus, the coefficient of thermal expansion (CTE) of the underfill, the out-of-plane CTE CTEz of the substrate, the thickness of the substrate, and the standoff height. When these parameters vary, the predicted life-times are calculated and some of the features of the results are explained. By comparing the predicted lifetimes of the two designs and the strain conditions under thermal loading, the local CTE mismatch has been found to be one of most important factors in defining the reliability of flip chips with microvias. [S1043-7398(00)01203-2]

Evaluation of Bare Die Chip Reliability Due to Underfill Materials During Mechanical Actuation and Thermal Cycling

2005 ◽  
Author(s):  
Arv Sinha
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Bond Line ◽  
Thermal Interface Material ◽  
High Power Density ◽  
The Finite Element Method ◽  
Chip Design ◽  
Thermal Interface ◽  
Ball Grid Arrays ◽  
Mechanical Actuation

Use of underfill materials to encapsulate ball grid arrays (BGAs) or chip scale packages (CSPs) have become very important in increasing the reliability of area array packages [1]. Underfill enhances the reliability of flip-chip devices by distributing the thermo-mechanical stresses [2, 3]. These stresses are generated due to mechanical actuation and coefficient of thermal expansion mismatch (CTE) [3]. They are required due to high power density of the current chip design to achieve fine bond line at the thermal interface material in order to dissipate heat. In this paper, details of reliability assessment using the finite element method and actual test data will be presented and discussed.

Effect of Underfill Thermomechanical Properties on Thermal Cycling Fatigue Reliability of Flip-Chip Ball Grid Array

2004 ◽  
Vol 126 (4) ◽  
pp. 560-564 ◽  
Author(s):  
Tong Hong Wang ◽  
Yi-Shao Lai ◽  
Jenq-Dah Wu
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Ball Grid Array ◽  
Thermomechanical Properties ◽  
Creep Model ◽  
Fatigue Reliability ◽  
Element Analysis ◽  
Dimensional Finite Element ◽  
Real Behavior ◽  
Thermal Cycling Fatigue

Plane two-dimensional finite element analysis was applied to study the effect of underfill thermomechanical properties on the potential of thermal fatigue failure for flip-chip ball grid array. Two-stage as well as constant thermomechanical properties of underfills were manipulated to represent extremes of practical underfills. The steady-state creep model was incorporated for the eutectic solder bump to represent its real behavior. It was found from the parametric studies that the underfill with high Young’s modulus, low coefficient of thermal expansion, and high glass transition temperature leads to the longest service life.

Shock and Vibration of Solder Bumped Flip Chip on Organic Coated Copper Boards

1996 ◽  
Vol 118 (2) ◽  
pp. 101-104 ◽  
Author(s):  
John Lau ◽  
Eric Schneider ◽  
Tom Baker
Keyword(s):  
Mathematical Analysis ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Plane Shock ◽  
Printed Circuit ◽  
Flip Chips ◽  
Solder Bumps ◽  
Out Of Plane ◽  
Vibration Tests

The reliability of solder bumped flip chips on organic coated copper (OCC) printed circuit board (PCB) has been studied by shock and vibration tests and a mathematical analysis. Two different chip sizes (7 mm and 14 mm on a side) have been studied, and the larger chips have many internal solder bumps. For the in-plane and out-of-plane and out-of-plane shock tests, the chips were assembled with and without underfill encapsulants. However, for the out-of-plane vibration tests all the chips were underfilled with epoxy.

Interactions Between Flip Chip Underfill and Solder Alloy

2010 ◽  
Vol 132 (3) ◽  
Author(s):  
D. Blass ◽  
P. Borgesen
Keyword(s):  
Solder Alloy ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Moisture Sensitivity ◽  
Complex Issue ◽  
Shock Testing ◽  
Out Of Plane ◽  
Level 3 ◽  
Mechanical Optimization

The effects of underfill selection on flip chip reliability were always a complex issue. Mechanical optimization of the underfill performance, achieved by the addition of appropriate fillers, is invariably a tradeoff between the adhesion and the coefficient of thermal expansion (CTE) and, thus, also between in-plane and out-of-plane stresses. Another critical concern is the degradation of the underfill in processing and/or long term exposure to operating temperatures and ambient humidity. This is strongly affected by the chemical compatibility with combinations of solder mask, chip passivation, and flux residues. The latter is believed to be responsible for our observation of interactions with the solder alloy, too. As for the effects of glass transition temperatures and CTE, we find materials that were close to optimum for eutectic SnPb to be very far from the best options for lead free joints. We report on two sets of systematic experiments. The first addressed the performance of combinations of underfills, no-clean fluxes, and solder alloys in a JEDEC level 3 moisture sensitivity test. The second one involved thermal shock testing of flip chip assemblies underfilled with one of five different materials after soldering with SnCu, SAC305, and SnPb.

Thermo-Mechanical Deformation and Stress Analysis of a Flip-Chip BGA

2003 ◽  
Author(s):  
J. D. Wu ◽  
Y. S. Lai ◽  
Y. L. Kuo ◽  
S. C. Hung ◽  
M.-H. R. Jen
Keyword(s):  
Flip Chip ◽  
Thermal Loading ◽  
Mechanical Deformation ◽  
Substrate Thickness ◽  
Inelastic Material ◽  
Out Of Plane ◽  
Cte Mismatch ◽  
Constitutive Response ◽  
Chip Carrier ◽  
Plane Displacement

This paper investigates thermo-mechanical deformation and stresses of a flip-chip package (FCBGA) with and without underfill materials. Chip carrier is a 2-2-2 build-up substrate with 40 × 40 mm2 dimension; while bump material employs Sn/37Pb eutectic solder. Temperature-dependent warpage (out-of-plane displacement) of a FCBGA is characterized via shadow moire´ technique. Results of warpage measurement reveal that packages do not follow the same path during thermal loading/unloading cycle (20-220-20 °C) for both FCBGA with and without underfills. This implies that both solder and underfill exhibit inelastic material response. Therefore, it is a necessity to consider nonlinear constitutive response of packaging materials when designing flip-chip packages. It is observed that FCBGA with underfill exhibit more warpage than packages without underfill due to higher CTE mismatch between underfills and silicon dies. Aspect of package geometry such as die-to-substrate thickness ratio is found to play important role in reducing package stresses. Especially, thinner die provides more direct impact to die stresses reduction than thinner substrate does.

Numerical and Experimental Study of Interface Delamination in Flip Chip BGA Package

2010 ◽  
Vol 132 (1) ◽  
Author(s):  
Hu Guojun ◽  
Andrew A. O. Tay ◽  
Luan Jing-En ◽  
Ma Yiyi
Keyword(s):  
Thermal Expansion ◽  
Material Properties ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Element Analysis ◽  
Epoxy Molding Compound ◽  
Molding Compound ◽  
Interface Delamination ◽  
Underfill Material ◽  
Die Thickness

The reliability of the flip chip package is strongly influenced by underfill, which has a much higher coefficient of thermal expansion (CTE) compared with other packaging materials and leads to large thermomechanical stresses developed during the assembly processes. Thermal expansion mismatch between different materials causes interface delamination between epoxy molding compound and silicon die as well as interface delamination between underfill and silicon die. The main objective of this study is to investigate the effects of underfill material properties, fillet height, and silicon die thickness on the interface delamination between epoxy molding compound and silicon die during a lead-free solder reflow process based on the modified virtual crack closure method. Based on finite element analysis and experiment study, it can be concluded that the energy release rates at reflow temperature are the suitable criteria for the estimation of interface delamination. Furthermore, it is found that underfill material properties (elastic modulus, CTE, and chemical cure shrinkage), fillet height, and silicon die thickness can be optimized to reduce the risk of interface delamination between epoxy molding compound and silicon die in the flip chip ball grid array package.

Application of an Epoxy Cap in a Flip-Chip Package Design

1989 ◽  
Vol 111 (1) ◽  
pp. 16-20 ◽  
Author(s):  
E. Suhir
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Preliminary Test ◽  
Elastic Stability ◽  
Thermally Induced ◽  
Package Design ◽  
Silicone Gels ◽  
Low Modulus ◽  
Supporting Frame

In order to combine the merits of epoxies, which provide good environmental and mechanical protection, and the merits of silicone gels, resulting in low stresses, one can use an encapsulation version, where a low modulus gel is utilized as a major encapsulant, while epoxy is applied as a protecting cap. Such an encapsulation version is currently under consideration, parallel with a metal cap version, for the Advanced VLSI package design which is being developed at AT&T Bell Laboratories. We recommend that the coefficient of thermal expansion for the epoxy be somewhat smaller than the coefficient of thermal expansion for the supporting frame. In this case the thermally induced displacements would result in a desirable tightness in the cap/frame interface. This paper is aimed at the assessment of stresses, which could arise in the supporting frame and in the epoxy cap at low temperatures. Also, the elastic stability of the cap, subjected to compression, is evaluated. The calculations were executed for the Advanced VLSI package design and for a Solder Test Vehicle (STV), which is currently used to obtain preliminary information regarding the performance of the candidate encapsulants. It is concluded that in order to avoid buckling of the cap, the latter should not be thinner than 15 mils (0.40 mm) in the case of VLSI package design and than 17.5 mils (0.45 mm) in the case of STV. At the same time, the thickness of the cap should not be greater than necessary, both for smaller stresses in the cap and for sufficient undercap space, required for wirebond encapsulation. The obtained formulas enable one to evaluate the actual and the buckling stresses. Preliminary test data, obtained by using STV samples, confirmed the feasibility of the application of an epoxy cap in a flip-chip package design.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Micro-Mechanical Deformation Analysis of Surface Laminar Circuit in Organic Flip-Chip Package: An Experimental Study

2000 ◽  
Vol 122 (4) ◽  
pp. 294-300 ◽  
Author(s):  
B. Han ◽  
P. Kunthong
Keyword(s):  
Flip Chip ◽  
Thermal Loading ◽  
Region Of Interest ◽  
Deformation Analysis ◽  
High Modulus ◽  
Displacement Fields ◽  
Complex Deformation ◽  
Mechanical Deformations ◽  
Displacement Sensitivity ◽  
Package Reliability

Thermo-mechanical deformations of microstructures in a surface laminar circuit (SLC) substrate are quantified by microscopic moire´ interferometry. Two specimens are analyzed; a bare SLC substrate and a flip chip package assembly. The specimens are subjected to a uniform thermal loading of ΔT=−70°C and the microscopic displacement fields are documented at the identical region of interest. The nano-scale displacement sensitivity and the microscopic spatial resolution obtained from the experiments provide a faithful account of the complex deformation of the surface laminar layer and the embedded microstructures. The displacement fields are analyzed to produce the deformed configuration of the surface laminar layer and the strain distributions in the microstructures. The high modulus of underfill produces a strong coupling between the chip and the surface laminar layer, which produces a DNP-dependent shear deformation of the layer. The effect of the underfill on the deformation of the microstructures is investigated and its implications on the package reliability are discussed. [S1043-7398(00)01304-9]

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