Application of an Epoxy Cap in a Flip-Chip Package Design

1989 ◽  
Vol 111 (1) ◽  
pp. 16-20 ◽  
Author(s):  
E. Suhir
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Preliminary Test ◽  
Elastic Stability ◽  
Thermally Induced ◽  
Package Design ◽  
Silicone Gels ◽  
Low Modulus ◽  
Supporting Frame

In order to combine the merits of epoxies, which provide good environmental and mechanical protection, and the merits of silicone gels, resulting in low stresses, one can use an encapsulation version, where a low modulus gel is utilized as a major encapsulant, while epoxy is applied as a protecting cap. Such an encapsulation version is currently under consideration, parallel with a metal cap version, for the Advanced VLSI package design which is being developed at AT&T Bell Laboratories. We recommend that the coefficient of thermal expansion for the epoxy be somewhat smaller than the coefficient of thermal expansion for the supporting frame. In this case the thermally induced displacements would result in a desirable tightness in the cap/frame interface. This paper is aimed at the assessment of stresses, which could arise in the supporting frame and in the epoxy cap at low temperatures. Also, the elastic stability of the cap, subjected to compression, is evaluated. The calculations were executed for the Advanced VLSI package design and for a Solder Test Vehicle (STV), which is currently used to obtain preliminary information regarding the performance of the candidate encapsulants. It is concluded that in order to avoid buckling of the cap, the latter should not be thinner than 15 mils (0.40 mm) in the case of VLSI package design and than 17.5 mils (0.45 mm) in the case of STV. At the same time, the thickness of the cap should not be greater than necessary, both for smaller stresses in the cap and for sufficient undercap space, required for wirebond encapsulation. The obtained formulas enable one to evaluate the actual and the buckling stresses. Preliminary test data, obtained by using STV samples, confirmed the feasibility of the application of an epoxy cap in a flip-chip package design.

Mechanical Behavior of Flip-Chip Encapsulants

1990 ◽  
Vol 112 (4) ◽  
pp. 327-332 ◽  
Author(s):  
E. Suhir ◽  
J. M. Segelken
Keyword(s):  
Mechanical Behavior ◽  
Flip Chip ◽  
Calculated Data ◽  
Chip Design ◽  
Package Design ◽  
Silicone Gels ◽  
Low Modulus ◽  
Stress Models ◽  
Final Selection ◽  
Selection Of

Requirements for the mechanical properties of the encapsulation material in a flip-chip design to prevent the solder and the encapsulation material itself from failure are presented on the basis of the developed analytical stress models, enabling one to predict the stresses caused by the expansion (contraction) mismatch of these materials. We evaluate and discuss the mechanical behavior of encapsulants for two encapsulation technologies: 1) encapsulant fills in the entire underchip space (silicone gels, epoxies); 2) encapsulant conformably coats the underchip surfaces (polyxylylene, polyimide). The calculations are carried out for an Advanced VLSI Package Design. The calculated data have indicated that low modulus silicone gel results in the lowest stresses. Polyxylylene should be considered as the second preference. Polyimide is also acceptable. Epoxies, however, could result in significant stresses in solder joints and therefore are less attractive. The final selection of the most feasible encapsulant should be done, of course, with consideration of all the electrical, chemical, and technological requirements.

Reliability of Sn-Ag-Cu Flip Chip Package with Underfill under Thermal Shock

2006 ◽  
Vol 510-511 ◽  
pp. 558-561 ◽  
Author(s):  
Bo In Noh ◽  
Seung Boo Jung
Keyword(s):  
Thermal Expansion ◽  
Thermal Shock ◽  
Solder Ball ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Fatigue Property ◽  
Electroless Nickel ◽  
Fatigue Properties ◽  
Electroless Nickel Immersion Gold ◽  
Better Than

Thermal fatigue properties of solder joints encapsulated with underfill were studied conducting thermal shock tests. Flip chip package with electroless nickel-immersion gold plated on FR-4 substrate and the Sn-3.0Ag-0.5Cu solder ball was used. The fatigue property of package with underfill was better than the package without it. The fatigue property of package with underfill which has a higher glass transition temperature (Tg) and lower coefficient of thermal expansion (CTE) was better than that of package with underfill with lower Tg and higher CTE.

Stress Distribution Effect on a Stacked-Die QFN Package Manufacturing Processes

2011 ◽  
Vol 462-463 ◽  
pp. 1273-1278
Author(s):  
I. Abdullah ◽  
Azman Jalar ◽  
Shahrum Abdullah ◽  
M.F. Rosle ◽  
Mohd Faridz Mod Yunoh
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
High Stress ◽  
Three Dimensional ◽  
Manufacturing Processes ◽  
Stress Effect ◽  
Package Design ◽  
Induced Stress ◽  
Die Attach ◽  
Low Modulus ◽  
Element Technique

In the last decade, failure of microelectronic devices has become a prominent field of research all across the world. The results of this of failure analysis allow an engineer to choose package geometries and materials which reduce the risk of failure. This paper is meant to relate the stress effect on material properties during Quad Flat No-Leads (QFN) stacked-die packages manufacturing processes. To achieve the study, the finite element technique was used to perform an extensive structural analysis on a QFN package design once it was verified by related experiments. A QFN unit was developed in three dimensional geometry with various materials be will simulated in order to determine the location of failure. The induced stress results were also measured in the maximum value, indicating the low modulus and coefficient of thermal expansion (CTE) in the packaging material were important for reducing high stress during the manufacturing stages. However, numerical simulation demonstrated that the stress developments increased exponentially when the die attach temperature increased. Therefore, the induced stress can be relieved by having high die attach process temperature with an adequate bonding force and time. It was vital to control the induced stress in package materials during die attachment process for ensuring the reliability level of QFN packages.

Development of Novel Filler Technology for No-Flow and Wafer Level Underfill Materials

2005 ◽  
Vol 127 (2) ◽  
pp. 77-85 ◽  
Author(s):  
Slawomir Rubinsztajn ◽  
Donald Buckley ◽  
John Campbell ◽  
David Esler ◽  
Eric Fiveland ◽  
...  
Keyword(s):  
Cost Reduction ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Organic Substrate ◽  
Operating Speed ◽  
Wafer Level ◽  
Package Design ◽  
Chip Technology ◽  
Package Size ◽  
Package Reliability

Flip chip technology is one of the fastest growing segments of electronic packaging with growth being driven by the demands such as cost reduction, increase of input/output density, package size reduction and higher operating speed requirements. Unfortunately, flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate, which leads to premature failures of the package. Package reliability can be improved by the application of an underfill. In this paper, we report the development of novel underfill materials utilizing nano-filler technology, which provides a previously unobtainable balance of low CTE and good solder joint formation.

Characterization of Epoxy-Functionalized Silsesquioxanes as Potential Underfill Encapsulants

1998 ◽  
Vol 519 ◽  
Author(s):  
E. K. Lin ◽  
C. R. Snyder ◽  
F. I. Mopsik ◽  
W. E. Wallace ◽  
W. L. Wu ◽  
...  
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Silica Particles ◽  
Critical Parameters ◽  
Organic Hybrid ◽  
Solder Bumps ◽  
The Difference ◽  
Electronics Packages

AbstractIn electronics packaging, underfill encapsulants are needed to improve package reliability in flip-chip devices. The underfill generally consists of an epoxy resin highly filled with silica particles and is designed to reduce the stress arising from the difference in the thermal expansion between the solder bumps and the substrate. Currently, concerns about the flow of the silica particles and surface phenomena are arising as electronics packages reduce in size. Newly developed epoxy-functionalized octameric silsesquioxanes provide an intriguing alternative to current formulations. These single-phase inorganic/organic hybrid materials may have properties similar to filled materials without the complications from the rheology of filled materials. The physical properties of the functionalized silsesquioxanes are measured with respect to the critical parameters for underfill materials. Measurements of properties such as the coefficient of thermal expansion and density are performed to evaluate the suitability of these materials as potential underfill encapsulants.

Numerical and Experimental Study of Interface Delamination in Flip Chip BGA Package

2010 ◽  
Vol 132 (1) ◽  
Author(s):  
Hu Guojun ◽  
Andrew A. O. Tay ◽  
Luan Jing-En ◽  
Ma Yiyi
Keyword(s):  
Thermal Expansion ◽  
Material Properties ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Element Analysis ◽  
Epoxy Molding Compound ◽  
Molding Compound ◽  
Interface Delamination ◽  
Underfill Material ◽  
Die Thickness

The reliability of the flip chip package is strongly influenced by underfill, which has a much higher coefficient of thermal expansion (CTE) compared with other packaging materials and leads to large thermomechanical stresses developed during the assembly processes. Thermal expansion mismatch between different materials causes interface delamination between epoxy molding compound and silicon die as well as interface delamination between underfill and silicon die. The main objective of this study is to investigate the effects of underfill material properties, fillet height, and silicon die thickness on the interface delamination between epoxy molding compound and silicon die during a lead-free solder reflow process based on the modified virtual crack closure method. Based on finite element analysis and experiment study, it can be concluded that the energy release rates at reflow temperature are the suitable criteria for the estimation of interface delamination. Furthermore, it is found that underfill material properties (elastic modulus, CTE, and chemical cure shrinkage), fillet height, and silicon die thickness can be optimized to reduce the risk of interface delamination between epoxy molding compound and silicon die in the flip chip ball grid array package.

Tailorable Thermal Expansion of Lightweight and Robust Dual-Constituent Triangular Lattice Material

2017 ◽  
Vol 84 (10) ◽  
Author(s):  
Kai Wei ◽  
Yong Peng ◽  
Weibin Wen ◽  
Yongmao Pei ◽  
Daining Fang
Keyword(s):  
Mechanical Properties ◽  
Thermal Expansion ◽  
Triangular Lattice ◽  
Coefficient Of Thermal Expansion ◽  
Bulk Material ◽  
Structure Design ◽  
Thermally Induced ◽  
Precise Control ◽  
Wide Range ◽  
Lattice Material

Current studies on tailoring the coefficient of thermal expansion (CTE) of materials focused on either exploring the composition of the bulk material or the design of composites which strongly depend on a few negative CTE materials or fibers. In this work, an approach to achieve a wide range of tailorable CTEs through a dual-constituent triangular lattice material is studied. Theoretical analyses explicitly reveal that through rational arrangement of commonly available positive CTE constituents, tailorable CTEs, including negative, zero, and large positive CTEs can be easily achieved. We experimentally demonstrate this approach through CTE measurements of the specimens, which were exclusively fabricated from common alloys. The triangular lattice material fabricated from positive CTE alloys is shown to yield large positive (41.6 ppm/°C), near-zero (1.9 ppm/°C), and negative (−32.9 ppm/°C) CTEs. An analysis of the collapse strength and stiffness ensures the robust mechanical properties. Moreover, hierarchal triangular lattice material is proposed, and with certain constituents, wide range of tailorable CTEs can be easily obtained through the rationally hierarchal structure design. The triangular lattice material presented here integrates tailorable CTEs, lightweight characteristic, and robust mechanical properties, and is very promising for engineering applications where precise control of thermally induced expansion is in urgently needed.

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