The impact of plasma-charging damage on the RF performance of deep-submicron MOSFET

2002 ◽  
Vol 23 (6) ◽  
pp. 309-311
Author(s):  
L. Pantisano ◽  
K.P. Cheung ◽  
P.J. Roussel ◽  
A. Paccagnella
Keyword(s):  
Deep Submicron ◽  
Rf Performance ◽  
The Impact

scholarly journals Numerical Evaluation of the Effect of Geometric Tolerances on the High-Frequency Performance of Graphene Field-Effect Transistors

Nanomaterials ◽  
2021 ◽  
Vol 11 (11) ◽  
pp. 3121
Author(s):  
Monica La Mura ◽  
Patrizia Lamberti ◽  
Vincenzo Tucci
Keyword(s):  
High Frequency ◽  
Communication Systems ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Geometrical Parameters ◽  
Effect Transistor ◽  
Rf Performance ◽  
The Impact

The interest in graphene-based electronics is due to graphene’s great carrier mobility, atomic thickness, resistance to radiation, and tolerance to extreme temperatures. These characteristics enable the development of extremely miniaturized high-performing electronic devices for next-generation radiofrequency (RF) communication systems. The main building block of graphene-based electronics is the graphene-field effect transistor (GFET). An important issue hindering the diffusion of GFET-based circuits on a commercial level is the repeatability of the fabrication process, which affects the uncertainty of both the device geometry and the graphene quality. Concerning the GFET geometrical parameters, it is well known that the channel length is the main factor that determines the high-frequency limitations of a field-effect transistor, and is therefore the parameter that should be better controlled during the fabrication. Nevertheless, other parameters are affected by a fabrication-related tolerance; to understand to which extent an increase of the accuracy of the GFET layout patterning process steps can improve the performance uniformity, their impact on the GFET performance variability should be considered and compared to that of the channel length. In this work, we assess the impact of the fabrication-related tolerances of GFET-base amplifier geometrical parameters on the RF performance, in terms of the amplifier transit frequency and maximum oscillation frequency, by using a design-of-experiments approach.

The impact of total ionizing dose on RF performance of 130 nm PD SOI I/O nMOSFETs

2021 ◽  
Vol 116 ◽  
pp. 114001
Author(s):  
Tiantian Xie ◽  
Hao Ge ◽  
Yinghuan Lv ◽  
Jing Chen
Keyword(s):  
Total Ionizing Dose ◽  
Rf Performance ◽  
The Impact

scholarly journals Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Satyam Shukla ◽  
Sandeep Singh Gill ◽  
Navneet Kaur ◽  
H. S. Jatana ◽  
Varun Nehru
Keyword(s):  
Process Parameters ◽  
Simulation Analysis ◽  
Oxide Thickness ◽  
Channel Length ◽  
Deep Submicron ◽  
Device Structure ◽  
Short Channel ◽  
20 Nm ◽  
The Impact ◽  
Fin Shape

Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (Ion/Ioff), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.

scholarly journals Monte Carlo Simulation of Non-Local Transport Effects in Strained Si on Relaxed Si1 – xGex Heterostructures

VLSI Design ◽  
1998 ◽  
Vol 8 (1-4) ◽  
pp. 253-256
Author(s):  
F. Gámiz ◽  
J. B. Roldán ◽  
J. A. López-Villanueva
Keyword(s):  
Monte Carlo ◽  
Performance Enhancement ◽  
Deep Submicron ◽  
Strained Si ◽  
Electron Transport Properties ◽  
Transport Effects ◽  
Non Local ◽  
Local Transport ◽  
Monte Carlo Simulator ◽  
The Impact

Electron transport properties of strained-Si on relaxed Si1 – xGex channel MOSFETs have been studied using a Monte Carlo simulator. The steady- and non-steady-state high-longitudinal field transport regimes have been described in detail. Electronvelocity- overshoot effects are studied in deep-submicron strained-Si MOSFETs, where they show an improvement over the performance of their normal silicon counterparts. The impact of the Si layer strain on the performance enhancement are described in depth in terms of microscopic magnitudes.

Low Frequency Noise Analysis in Advanced CMOS Devices

2011 ◽  
Vol 324 ◽  
pp. 441-444 ◽  
Author(s):  
Jalal Jomaah ◽  
Majida Fadlallah ◽  
Gerard Ghibaudo
Keyword(s):  
Experimental Data ◽  
Noise Analysis ◽  
Low Frequency ◽  
Deep Submicron ◽  
Electrical Noise ◽  
Frequency Noise ◽  
Low Frequency Noise ◽  
Noise Sources ◽  
The Impact ◽  
Mobility Fluctuations

A review of recent results concerning the low frequency noise in modern CMOS devices is given. The approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are illustrated through experimental data obtained on advanced CMOS generations. Furthermore, the impact on the electrical noise of the shrinking of CMOS devices in the deep submicron range is also shown.

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