In-Memory Computing on Resistive RAM Systems Using Majority Operation

Memristors can be used to build nonvolatile memory systems with in-memory computing (IMC) capabilities. A number of prior works demonstrate the design of an IMC-capable memory macro using a memristor crossbar. However, read disturbance limits the use of such memory systems built using a 0-transistor, 1-RRAM (0T1R) structure that suffers from the sneak path problem. In this paper, we introduce a scheme for both memory and logic operations using the 1-transistor, 1-RRAM (1T1R) memristor crossbar, which effectively mitigates the read disturbance problem. The memory array is designed using nMOS transistors and the VTEAM memristor model. The peripheral circuitry like decoders, voltage multiplexers, and sense amplifiers is designed using a 45[Formula: see text]nm CMOS technology node. We introduce a mapping technique to realize arbitrary logic functions using Majority (MAJ) gate operations in the 1T1R crossbar. Through extensive experimentation on benchmark functions, it has been found that the proposed mapping method gives an improvement of 65% or more in terms of the number of time steps required, and 59% or more in terms of energy consumption as compared to some of the recent methods.

Electronically Tunable Full Wave Precision Rectifier Using DVCCTAs

This work presents a voltage mode scheme of a full-wave precision rectifier circuit using an analog building block differential voltage current conveyor transconductance amplifier (DVCCTA) including five NMOS transistors. The proposed design is essentially suited for low voltage and high-frequency input signals. The operation of the proposed rectifier design depends upon the region of operation of NMOS transistors. The output waveform of the presented rectifier design can be made electronically tunable by controlling the bias voltage. The functional correctness and verification of the presented design are performed using 0.25-µm TSMC technology under the supply voltage of ±1.5 V. The absence of a resistor leads to a minimal parasitic effect. To obtain further insight on the robustness of the circuit, a Monte Carlo simulation and corner analysis are also presented. The circuit is verified experimentally by incorporating a breadboard model with the help of commercially available ICs CA3080 (operational transconductance amplifier) and AD844AN (current feedback operational amplifier) and offers remarkable compliance with both theoretical and simulation outcomes. The presented design has been laid out on Cadence virtuoso, which consumes a chip area of 9044 µm2.

Single EXCCII-Based Analog Multiplier Structure

A simple analog multiplier circuit employing one current-mode active building block (ABB) and two n-channel metal-oxide semiconductor (NMOS) transistors is presented in this paper. The used ABB is extra-X second generation current conveyor. The used NMOS transistors are operated in triode region. The circuit has appropriate impedance level at the input and output terminals. Some other key features of the proposed circuit are as follows: suitable to integrated circuit fabrication, good dynamic range and low operating power supplies. The nonideal effects of extra-X second generation current conveyor on the proposed circuit are studied. Additionally, the layout of the proposed circuit is developed using Cadence VIRTUOSO Analog Design Environment with gpdk 0.18[Formula: see text][Formula: see text]m technology and post layout simulation results are given to verify the theoretical aspects.